Setting
External Address Pins
Bus
Memory AMX AMX AMX AMX Output
A1 to
A8
Width Type
3
2
1
0
Timing
A9
A10 A11 A12 A13 A14 A15 A16
2M ×
0
1
0
1
Column A1 to A9
address A8
A10 L/H 3 A12 A22 A23 4 A24
4
*
*
*
16bits ×
2
2
2
*
4banks
4
*
*
Row
address A17
A10 toA18 A19 A20 A21 A22 A23 4 A24
A10 L/H 3 A12 A21 A22 4 A15
4
*
*
*
1M ×
0
0
1
1
0
0
0
1
Column A1 to A9
address A8
16bits ×
*
4banks
4
*
*
Row
A 9 to A17 A18 A19 A20 A21 A22 4 A23
address A16
A10 L/H 3 A12 A22 A23 4 A24
4
*
*
*
2M ×
8bits ×
4banks
Column A1 to A9
address A8
*
4
A10 toA18 A19 A20 A21 A22 A23 4 A24
*
*
Row
address A17
Notes: 1. Only RAL3L or CASL is output.
2. When addresses are upper 32 Mbytes, RAS3U or CASU is output.
When addresses are lower 32 Mbytes, RAS3L or CASL is output.
3. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
4. Bank address specification
Rev. 5.00, 09/03, page 280 of 760
RENESAS [ RENESAS TECHNOLOGY CORP ]
