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HD6417709SF133B 参数 Datasheet PDF下载

HD6417709SF133B图片预览
型号: HD6417709SF133B
PDF下载: 下载PDF文件 查看货源
内容描述: 瑞萨32位RISC单片机超级RISC引擎族/ SH7700系列 [Renesas 32-Bit RISC Microcomputer Super RISC engine Family/SH7700 Series]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 807 页 / 4409 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Table 10.14 Example of Correspondence between SH7709S and Synchronous DRAM  
Address Pins (AMX [3:0] = 0100 (32-Bit Bus Width))  
SH7709S Address Pin  
RAS Cycle  
A23  
Synchronous DRAM Address Pin  
Function  
CAS Cycle  
A23  
A22  
A13  
L/H  
A11  
A10  
A9  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
A13(BA1)  
A12(BA0)  
A11  
BANK select bank address  
A22  
A21  
A20  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
Address  
A10  
Address precharge setting  
Address  
A9  
A8  
A7  
A8  
A8  
A6  
A7  
A7  
A5  
A6  
A6  
A4  
A5  
A5  
A3  
A4  
A4  
A2  
A3  
A3  
A1  
A2  
A2  
A0  
A1  
A1  
Not used  
Not used  
A0  
A0  
A0  
Burst Read: In the example in figure 10.15 it is assumed that four 2M × 8-bit synchronous  
DRAMs are connected and a 32-bit data width is used, and the burst length is 1. Following the Tr  
cycle in which ACTV command output is performed, a READ command is issued in the Tc1, Tc2,  
and Tc3 cycles, and a READA command in the Tc4 cycle, and the read data is accepted at the  
rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is  
used to wait for completion of auto-precharge based on the READA command inside the  
synchronous DRAM; no new access command can be issued to the same bank during this cycle,  
but access to synchronous DRAM for another area is possible. In the SH7709S, the number of Tpc  
cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the  
same synchronous DRAM during this interval.  
The example in figure 10.14 shows the basic cycle. To connect low-speed synchronous DRAM,  
the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV  
command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the  
RCD bits in MCR, with values of 0 to 3 specifying 1 to 4 cycles, respectively. In case of 2 or more  
cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is inserted  
between the Tr cycle and the Tc cycle. The number of cycles from READ and READA command  
output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3 cycles  
Rev. 5.00, 09/03, page 281 of 760  
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