Table 21.3 Configuration of the Boundary Scan Register (3)
No. Pin Name
118 :(8/&$68/DQM5
117 :(8/&$68/DQM5
116 CKE
Type
CTL
OUT
CTL
OUT
IN
No. Pin Name
Type
IN
No. Pin Name
Type
CTL
OUT
IN
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
D13
D13
D13
D1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
D35
D35
D44
D44
D44
D34
D34
D34
D45
D45
D45
D33
D33
D33
D46
D46
D46
D32
D32
D32
D47
D47
D47
5'5
5'5
%6
CTL
OUT
IN
115 CKE
CTL
OUT
IN
114 D7
D1
CTL
OUT
IN
113 D7
CTL
OUT
IN
D1
112 D7
D14
D14
D14
D0
CTL
OUT
IN
111 D8
CTL
OUT
IN
110 D8
CTL
OUT
IN
109 D8
CTL
OUT
IN
108 %5(4/%6$&.
107 %$&./%65(4
106 %$&./%65(4
105 D6
D0
CTL
OUT
IN
CTL
OUT
IN
D0
D15
D15
D15
D39
D39
D39
D40
D40
D40
D38
D38
D38
D41
D41
D41
D37
D37
D37
D42
D42
D42
D36
D36
D36
D43
D43
D43
D35
CTL
OUT
IN
CTL
OUT
IN
104 D6
CTL
OUT
IN
103 D6
CTL
OUT
IN
102 D9
CTL
OUT
IN
101 D9
CTL
OUT
IN
100 D9
CTL
OUT
IN
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
D5
CTL
OUT
IN
D5
CTL
OUT
IN
D5
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
CTL
OUT
IN
D10
D10
D10
D4
CTL
OUT
IN
CTL
OUT
IN
CTL
OUT
IN
D4
CTL
OUT
IN
%6
D4
CS6
CS6
CS5
CS5
CS4
CS4
CS1
CS1
CS0
CS0
5'<
D11
D11
D11
D3
CTL
OUT
IN
CTL
OUT
IN
8
CTL
OUT
IN
7
D3
CTL
OUT
IN
6
D3
5
D12
D12
D12
D2
CTL
OUT
IN
4
CTL
OUT
IN
3
2
CTL
OUT
IN
1
D2
CTL
OUT
to TDO
D2
Note: CTL is an active-low signal. The relevant pin is driven to the OUT state when CTL is set LOW.
Rev. 6.0, 07/02, page 809 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
