Table 1.4 Pin Functions (cont)
Memory Interface
Pin
No. No. Pin Name I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
89 N9
90 U9
A7
O
O
Address
CKIO
Clock output
CKIO
CKIO
91 M9 VDDQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
92 P9
93 T9
VSSQ
CKIO2
O
O
O
O
CKIO*
94 M10 A6
Address
Address
Address
95 U10 A5
96 N10 A4
97 R10 VDDQ
98 P10 VSSQ
99 T10 A3
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
O
Address
Address
100 M11 A2
101 U11 DRAK1
DMAC1 request
acknowledge
102 N11 DRAK0
O
DMAC0 request
acknowledge
103 R11 VDDQ
104 N12 VSSQ
105 U12 &66
106 P11 &65
107 T11 VDD
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
Chip select 3
Chip select 2
&66
&65
(&66)
(&65)
&66
&65
&66
&65
Power Internal VDD
(1.5 V)
108 N13 VSS
Power Internal GND
(0 V)
109 R12 5$6
O
O
5$6
5$6
5$6
&$6
110 P12 5'/&$66/
Read/&$6/
2(
2(
)5$0(
)5$0(
)5$0(
111 U13 VDDQ
112 P13 VSSQ
113 T12 RD/:5
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
Read/write
RD/:5 RD/:5 RD/:5
RD/:5
114 R15 :(5/&$65/ O
D23–D16 select
signal
:(5
&$65
DQM2 ,&,25'
DQM2/
,&,25'
115 R13 :(6/&$66/ O
D31–D24 select
signal
:(6
&$66
DQM3 ,&,2:5
DQM3/
,&,2:5
Rev. 6.0, 07/02, page 34 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
