Table 1.4 Pin Functions (cont)
Memory Interface
Pin
No. No. Pin Name I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
198 D11 VSS
Power Internal GND
(0 V)
199 C11 A18
200 F12 A19
201 B11 VDDQ
202 E11 VSSQ
203 A11 A20
204 F11 A21
205 C10 A22
206 D10 A23
207 A10 VDDQ
208 E10 VSSQ
209 B10 A24
210 F10 A25
O
O
Address
Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
O
O
Address
Address
Address
Address
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
Address
Address
211 C9
MD3/&(5$ I/O
Mode/
PCMCIA-CE
MD3
MD4
&(5$
&(5%
212 E9
MD4/&(5% I/O
Mode/
PCMCIA-CE
213 A9
214 F9
215 D9
VDDQ
VSSQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
MD5/5$65 I/O
Mode/5$6
MD5
5$65
(DRAM)
216 B9
217 F8
DACK0
DACK1
O
O
O
DMAC0 bus
acknowledge
DMAC1 bus
acknowledge
218 A8
219 E8
220 C8
221 D8
222 B8
223 F7
224 A7
A0
Address
VDDQ
VSSQ
A1
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
O
I
Address
Status
Status
STATUS0
STATUS1
MD6/
,2,649
Mode/,2,649
MD6
,2,649
(PCMCIA)
225 E7
226 C7
VDDQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
VSSQ
Rev. 6.0, 07/02, page 38 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
