Table 1.4 Pin Functions (cont)
Memory Interface
Pin
No. No. Pin Name I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
31 J6
32 J4
33 J2
34 K6
35 K1
36 K5
37 K3
38 K4
39 K2
40 L6
41 L1
42 L5
43 L3
VSSQ
D41
Power IO GND (0 V)
I/O
I/O
I/O
I/O
Data/port
Data/port
Data/port
Data/port
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
(Port)
D38
D40
D39
VDDQ
VSSQ
D15
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O
I/O
I/O
I/O
Data
Data
Data
Data
A15
A0
D0
D14
A14
A1
D1
VDDQ
VSSQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
44 M5 D13
45 M1 D2
I/O
I/O
Data
Data
A13
A2
46 L4
47 L2
48 N5
VDD
VSS
D12
Power Internal VDD
(1.5 V)
Power Internal GND
(0 V)
I/O
I/O
Data
Data
A12
A3
49 M3 D3
50 M4 VDDQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
51 N1
52 N4
VSSQ
D11
I/O
I/O
I/O
I/O
Data
Data
Data
Data
A11
A4
53 M2 D4
54 R3
55 N3
56 P3
57 P1
58 U1
59 R1
60 T1
D10
A10
A5
D5
VDDQ
VSSQ
D9
Power IO VDD (3.3 V)
Power IO GND (0 V)
I/O
I/O
O
Data
Data
A9
A6
D6
%$&./
Bus
%65(4
acknowledge/
bus request
Rev. 6.0, 07/02, page 32 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
