Table 1.3 Pin Functions (cont)
Memory Interface
Pin
No.
Pin Name
I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
194
TDO
O
Data out
(H-UDI)
195
196
VDD
VSS
Power Internal VDD
Power Internal GND
(0 V)
197
198
199
200
201
202
203
204
205
206
207
208
TMS
TCK
TDI
I
I
I
I
Mode (H-UDI)
Clock (H-UDI)
Data in (H-UDI)
Reset (H-UDI)
7567
VDD-PLL2 Power PLL2 VDD (3.3V)
VSS-PLL2 Power PLL2 GND (0V)
VDD-PLL1 Power PLL1 VDD (3.3V)
VSS-PLL1
VDD-CPG
VSS-CPG
XTAL
Power PLL1 GND (0V)
Power CPG VDD (3.3V)
Power CPG GND (0V)
O
I
Crystal resonator
EXTAL
External input
clock/crystal
resonator
I:
Input
O:
I/O:
Output
Input/output
Power: Power supply
Notes: 1. Except in hardware standby mode, supply power to all power pins. In hardware standby
mode, supply power to RTC as a minimum.
2. Power must be supplied to VDD-PLL1/2 and VSS-PLL1/2 regardless of whether or not
the on-chip PLL circuits are used.
3. Power must be supplied to VDD-CPG and VSS-CPG regardless of whether or not the
on-chip crystal resonator is used.
4. Power must be supplied to VDD-RTC and VSS-RTC regardless of whether or not the
on-chip RTC is used.
5. VSSQ, VSS, VSS-RTC, VSS-PLL1/2, and VSS-CPG are connected inside the package.
6. In the SH7750S and SH7750R, at least the RTC power supply must be supplied in
hardware standby mode.
7. The 5'5, RD/:55, CKIO2, and &.,25(1% pins are not provided on the QFP
package.
8. For a QFP package, the maximum operating frequency of the external bus is 84 MHz.
*
Hardware standby request (SH7750S and SH7750R). In the SH7750, pull up to 3.3 V.
Rev. 6.0, 07/02, page 30 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
