Table 1.4 Pin Functions (cont)
Memory Interface
Pin
No. No. Pin Name I/O
Function
Reset
SRAM DRAM SDRAM PCMCIA MPX
61 R2
%5(4/
I
Bus request/bus
acknowledge
%6$&.
62 T3
63 U2
64 R4
D8
I/O
I/O
O
Data
Data
A8
D7
A7
CKE
Clock output
enable
CKE
65 T5
66 T2
67 R5
VDDQ
VSSQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
:(8/&$68/ O
D47–D40 select
signal
:(8
:(7
:(4
:(3
&$68
&$67
&$64
&$63
DQM5
DQM5
68 P5
69 U5
70 P6
:(7/&$67/ O
D39–D32 select
signal
DQM4
DQM4
:(4/&$64/ O
D15–D8 select
signal
DQM1 :(4
DQM0
DQM1
:(3/&$63/ O
D7–D0 select
signal
DQM0
71 R6
72 P4
73 T6
74 N6
75 U6
76 P7
A17
O
Address
VDDQ
VSSQ
A16
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
Address
Address
A15
VDD
Power Internal VDD
(1.5 V)
77 R7
VSS
Power Internal GND
(0 V)
78 M6 A14
O
O
Address
Address
79 T7
80 N7
81 U7
82 R8
83 P8
84 U8
85 N8
86 T8
A13
VDDQ
VSSQ
A12
Power IO VDD (3.3 V)
Power IO GND (0 V)
O
O
O
Address
Address
Address
A11
A10
VDDQ
VSSQ
Power IO VDD (3.3 V)
Power IO GND (0 V)
87 M8 A9
88 R9 A8
O
O
Address
Address
Rev. 6.0, 07/02, page 33 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
