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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Error handling  
ORER = 1?  
No  
Yes  
Overrun error handling  
Clear ORER flag in SCSSR1 to 0  
End  
Figure 15.21 Sample Serial Reception Flowchart (2)  
In serial reception, the SCI operates as described below.  
1. The SCI performs internal initialization in synchronization with serial clock input or output.  
2. The received data is stored in SCRSR1 in LSB-to-MSB order.  
After reception, the SCI checks whether the RDRF flag is 0, indicating that the receive data  
can be transferred from SCRSR1 to SCRDR1.  
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in SCRDR1. If  
a receive error is detected in the error check, the operation is as shown in table 15.11.  
Neither transmit nor receive operations can be performed subsequently when a receive error  
has been found in the error check.  
Also, as the RDRF flag is not set to 1 when receiving, the flag must be cleared to 0.  
3. If the RIE bit in SCRSR1 is set to 1 when the RDRF flag changes to 1, a receive-data-full  
interrupt (RXI) request is generated. If the RIE bit in SCRSR1 is set to 1 when the ORER flag  
changes to 1, a receive-error interrupt (ERI) request is generated.  
Figure 15.22 shows an example of SCI operation in reception.  
Rev. 6.0, 07/02, page 648 of 986  
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