15.4
SCI Interrupt Sources and DMAC
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request.
Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt sources
can be enabled or disabled with the TIE, RIE, and TEIE bits in SCRSR1, and the EIO bit in
SCSPTR1. Each kind of interrupt request is sent to the interrupt controller independently.
When the TDRE flag in the serial status register (SCSSR1) is set to 1, a TDR-empty request is
generated separately from the interrupt request. A TDR-empty request can activate the direct
memory access controller (DMAC) to perform data transfer. The TDRE flag is cleared to 0
automatically when a write to the transmit data register (SCTDR1) is performed by the DMAC.
When the RDRF flag in SCSSR1 is set to 1, an RDR-full request is generated separately from the
interrupt request. An RDR-full request can activate the DMAC to perform data transfer.
The RDRF flag is cleared to 0 automatically when a receive data register (SCRDR1) read is
performed by the DMAC.
When the ORER, FER, or PER flag in SCSSR1 is set to 1, an ERI interrupt request is generated.
The DMAC cannot be activated by an ERI interrupt request. When receive data processing is to be
carried out by the DMAC and receive error handling is to be performed by means of an interrupt
to the CPU, set the RIE bit to 1 and also set the EIO bit in SCSPTR1 to 1 so that an interrupt error
occurs only for a receive error. If the EIO bit is cleared to 0, interrupts to the CPU will be
generated even during normal data reception.
When the TEND flag in SCSSR1 is set to 1, a TEI interrupt request is generated. The DMAC
cannot be activated by a TEI interrupt request.
A TXI interrupt indicates that transmit data can be written, and a TEI interrupt indicates that the
transmit operation has ended.
Table 15.12 SCI Interrupt Sources
Interrupt
Source
DMAC
Activation
Priority on
Reset Release
Description
ERI
RXI
TXI
TEI
Receive error (ORER, FER, or PER)
Receive data register full (RDRF)
Transmit data register empty (TDRE)
Transmit end (TEND)
Not possible High
Possible
Possible
↑
↓
Not possible Low
See section 5, Exceptions, for the priority order and relation to non-SCI interrupts.
Rev. 6.0, 07/02, page 651 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
