欢迎访问ic37.com |
会员登录 免费注册
发布采购

HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
 浏览型号HD6417750SBP200的Datasheet PDF文件第698页浏览型号HD6417750SBP200的Datasheet PDF文件第699页浏览型号HD6417750SBP200的Datasheet PDF文件第700页浏览型号HD6417750SBP200的Datasheet PDF文件第701页浏览型号HD6417750SBP200的Datasheet PDF文件第703页浏览型号HD6417750SBP200的Datasheet PDF文件第704页浏览型号HD6417750SBP200的Datasheet PDF文件第705页浏览型号HD6417750SBP200的Datasheet PDF文件第706页  
1. SCI status check and transmit data  
write:  
Start of transmission/reception  
Read TDRE flag in SCSSR1  
Read SCSSR1 and check that the  
TDRE flag is set to 1, then write  
transmit data to SCTDR1 and clear  
the TDRE flag to 0. Transition of the  
TDRE flag from 0 to 1 can also be  
identified by a TXI interrupt.  
No  
TDRE = 1?  
Yes  
2. Receive error handling:  
If a receive error occurs, read the  
ORER flag in SCSSR1 , and after  
performing the appropriate error  
handling, clear the ORER flag to 0.  
Transmission/reception cannot be  
resumed if the ORER flag is set to 1.  
Write transmit data  
to SCTDR1 and clear TDRE flag  
in SCSSR1 to 0  
3. SCI status check and receive data  
read:  
Read ORER flag in SCSSR1  
Read SCSSR1 and check that the  
RDRF flag is set to 1, then read the  
receive data in SCRDR1 and clear the  
RDRF flag to 0. Transition of the  
RDRF flag from 0 to 1 can also be  
identified by an RXI interrupt.  
Yes  
ORER = 1?  
No  
Error handling  
4. Serial transmission/reception  
continuation procedure:  
Read RDRF flag in SCSSR1  
To continue serial transmission/  
reception, finish reading the RDRF  
flag, reading SCRDR1, and clearing  
the RDRF flag to 0, before the MSB  
(bit 7) of the current frame is received.  
Also, before the MSB (bit 7) of the  
current frame is transmitted, read 1  
from the TDRE flag to confirm that  
writing is possible, then write data to  
SCTDR1 and clear the TDRE flag to  
0.  
No  
RDRF = 1?  
Yes  
Read receive data in SCRDR1,  
and clear RDRF flag  
in SCSSR1 to 0  
No  
(Checking and clearing of the TDRE  
flag is automatic when the DMAC is  
activated by a transmit-data-empty  
interrupt (TXI) request, and data is  
written to SCTDR1. Similarly, the  
RDRF flag is cleared automatically  
when the DMAC is activated by a  
receive-data-full interrupt (RXI)  
request and the SCRDR1 value is  
read.)  
All data transferred?  
Yes  
Clear TE and RE bits  
in SCRSR1 to 0  
End of transmission/reception  
Note: When switching from transmit or receive operation to simultaneous transmit and receive  
operations, first clear the TE bit and RE bit to 0, then set both these bits to 1.  
Figure 15.23 Sample Flowchart for Serial Data Transmission and Reception  
Rev. 6.0, 07/02, page 650 of 986  
 复制成功!