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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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In serial transmission, the SCI operates as described below.  
1. The SCI monitors the TDRE flag in SCSSR1. When TDRE is cleared to 0, the SCI recognizes  
that data has been written to SCTDR1, and transfers the data from SCTDR1 to SCTSR1.  
2. After transferring data from SCTDR1 to SCTSR1, the SCI sets the TDRE flag to 1 and starts  
transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI)  
request is generated.  
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an  
external clock has been specified, data is output synchronized with the input clock.  
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with  
the MSB (bit 7).  
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).  
If the TDRE flag is cleared to 0, data is transferred from SCTDR1 to SCTSR1, and serial  
transmission of the next frame is started.  
If the TDRE flag is set to 1, the TEND flag in SCSSR1 is set to 1, the MSB (bit 7) is sent, and  
the TxD pin maintains its state.  
If the TEIE bit in SCSCR1 is set to 1 at this time, a transmit-end interrupt (TEI) request is  
generated.  
4. After completion of serial transmission, the SCK pin is fixed high.  
Figure 15.20 shows an example of SCI operation in transmission.  
Transfer  
direction  
Serial clock  
LSB  
Bit 0  
MSB  
Bit 7  
Bit 1  
Bit 0  
Bit 1  
Bit 6  
Bit 7  
Serial data  
TDRE  
TEND  
Data written to SCTDR1  
and TDRE flag cleared to  
0 in TXI interrupt handler  
TXI interrupt  
request  
TEI interrupt  
request  
TXI interrupt  
request  
One frame  
Figure 15.20 Example of SCI Transmit Operation  
Rev. 6.0, 07/02, page 646 of 986  
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