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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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In serial communication, one character consists of data output starting with the LSB and ending  
with the MSB. After the MSB is output, the transmission line holds the MSB state.  
In synchronous mode, the SCI receives data in synchronization with the falling edge of the serial  
clock.  
Data Transfer Format  
A fixed 8-bit data format is used. No parity or multiprocessor bits are added.  
Clock  
Either an internal clock generated by the on-chip baud rate generator or an external serial clock  
input at the SCK pin can be selected, according to the setting of the C/$ bit in SCSMR1 and the  
CKE1 and CKE0 bits in SCSCR1. For details of SCI clock source selection, see table 15.9.  
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.  
Eight serial clock pulses are output in the transfer of one character, and when no transfer is  
performed the clock is fixed high. In reception only, if an on-chip clock source is selected, clock  
pulses are output while RE = 1. When the last data is received, RE should be cleared to 0 before  
the end of bit 7.  
Data Transfer Operations  
SCI Initialization (Synchronous Mode): Before transmitting and receiving data, it is necessary  
to clear the TE and RE bits in SCSCR1 to 0, then initialize the SCI as described below.  
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to  
0 before making the change using the following procedure. When the TE bit is cleared to 0, the  
TDRE flag is set to 1 and SCTSR1 is initialized. Note that clearing the RE bit to 0 does not change  
the contents of the RDRF, PER, FER, and ORER flags, or the contents of SCRDR1.  
Figure 15.18 shows a sample SCI initialization flowchart.  
Rev. 6.0, 07/02, page 643 of 986  
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