15.2.7 Serial Status Register (SCSSR1)
Bit:
7
TDRE
1
6
RDRF
0
5
ORER
0
4
FER
0
3
PER
0
2
TEND
1
1
MPB
—
0
MPBT
0
Initial value:
R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written, to clear the flag.
R
R
R/W
SCSSR1 is an 8-bit register containing status flags that indicate the operating status of the SCI,
and multiprocessor bits.
SCSSR1 can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SCSSR1 is initialized to H'84 by a power-on reset or manual reset, in standby mode, and in the
module standby state.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
SCTDR1 to SCTSR1 and the next serial transmit data can be written to SCTDR1.
Bit 7: TDRE
Description
0
Valid transmit data has been written to SCTDR1
[Clearing conditions]
•
•
When 0 is written to TDRE after reading TDRE = 1
When data is written to SCTDR1 by the DMAC
1
There is no valid transmit data in SCTDR1
[Setting conditions]
(Initial value)
•
•
•
Power-on reset, manual reset, standby mode, or module standby
When the TE bit in SCSCR1 is 0
When data is transferred from SCTDR1 to SCTSR1 and data can be
written to SCTDR1
Rev. 6.0, 07/02, page 605 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
