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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock  
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and  
CKE0 bits determines whether the SCK pin functions as the serial clock output pin or the serial  
clock input pin.  
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in  
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode and in the case of  
external clock operation (CKE1 = 1). The CKE1 and CKE0 bits must be set before determining  
the SCI’s operating mode with SCSMR1.  
For details of clock source selection, see table 15.9 in section 15.3, Operation.  
Bit 1: CKE1  
Bit 0: CKE0  
Description  
0
0
Asynchronous mode  
Internal clock/SCK pin functions as  
1
*
input pin (input signal ignored)  
Synchronous mode  
Asynchronous mode  
Synchronous mode  
Asynchronous mode  
Synchronous mode  
Asynchronous mode  
Synchronous mode  
Internal clock/SCK pin functions as  
1
*
serial clock output  
1
0
1
Internal clock/SCK pin functions as  
2
*
clock output  
Internal clock/SCK pin functions as  
serial clock output  
1
External clock/SCK pin functions as  
3
*
clock input  
External clock/SCK pin functions as  
serial clock input  
External clock/SCK pin functions as  
3
*
clock input  
External clock/SCK pin functions as  
serial clock input  
Notes: *1 Initial value  
*2 Outputs a clock of the same frequency as the bit rate.  
*3 Inputs a clock with a frequency 16 times the bit rate.  
Rev. 6.0, 07/02, page 604 of 986  
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