15.2.8 Serial Port Register (SCSPTR1)
Bit:
7
EIO
0
6
—
0
5
—
0
4
—
0
3
2
1
0
SPB1IO SPB1DT SPB0IO SPB0DT
Initial value:
R/W:
0
—
0
—
R/W
—
—
—
R/W
R/W
R/W
R/W
SCSPTR1 is an 8-bit readable/writable register that controls input/output and data for the port pins
multiplexed with the serial communication interface (SCI) pins. Input data can be read from the
RxD pin, output data written to the TxD pin, and breaks in serial transmission/reception
controlled, by means of bits 1 and 0. SCK pin data reading and output data writing can be
performed by means of bits 3 and 2. Bit 7 controls enabling and disabling of the RXI interrupt.
SCSPTR1 can be read or written to by the CPU at all times. All SCSPTR1 bits except bits 2 and 0
are initialized to H'00 by a power-on reset or manual reset; the value of bits 2 and 0 is undefined.
SCSPTR1 is not initialized in the module standby state or standby mode.
Bit 7—Error Interrupt Only (EIO): When the EIO bit is 1, an RXI interrupt request is not sent
to the CPU even if the RIE bit is set to 1. When the DMAC is used, this setting means that only
ERI interrupts are handled by the CPU. The DMAC transfers read data to memory or another
peripheral module. This bit specifies enabling or disabling of the RXI interrupt.
Bit 7: EIO
Description
0
1
When the RIE bit is 1, RXI and ERI interrupts are sent to INTC(Initial value)
When the RIE bit is 1, only ERI interrupts are sent to INTC
Bits 6 to 4—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 3—Serial Port Clock Port I/O (SPB1IO): Specifies serial port SCK pin input/output. When
the SCK pin is actually set as a port output pin and outputs the value set by the SPB1DT bit, the
C/$ bit in SCSMR1 and the CKE1 and CKE0 bits in SCSCR1 should be cleared to 0.
Bit 3: SPB1IO
Description
0
1
SPB1DT bit value is not output to the SCK pin
SPB1DT bit value is output to the SCK pin
(Initial value)
Rev. 6.0, 07/02, page 609 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
