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HD6417750SBP200 参数 Datasheet PDF下载

HD6417750SBP200图片预览
型号: HD6417750SBP200
PDF下载: 下载PDF文件 查看货源
内容描述: 的SuperH RISC引擎 [SuperH RISC engine]
分类和应用: 外围集成电路时钟
文件页数/大小: 1039 页 / 6201 K
品牌: RENESAS [ RENESAS TECHNOLOGY CORP ]
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Bit 2—Transmit End (TEND): Indicates that there is no valid data in SCTDR1 when the last bit  
of the transmit character is sent, and transmission has been ended.  
The TEND flag is read-only and cannot be modified.  
Bit 2: TEND  
Description  
0
Transmission is in progress  
[Clearing conditions]  
When 0 is written to TDRE after reading TDRE = 1  
When data is written to SCTDR1 by the DMAC  
1
Transmission has been ended  
[Setting conditions]  
(Initial value)  
Power-on reset, manual reset, standby mode, or module standby  
When the TE bit in SCSCR1 is 0  
When TDRE = 1 on transmission of the last bit of a 1-byte serial transmit  
character  
Bit 1—Multiprocessor Bit (MPB)*: This bit is read-only and cannot be written to. The read  
value is undefined.  
Note: * This bit is prepared for storing a multi-processor bit in the received data when the receipt  
is carried out with a multi-processor format in asynchronous mode. This bit does not  
function correctly in this LSI. However, do not use the read value from this bit.  
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a  
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to  
the transmit data.  
The MPBT bit setting is invalid in synchronous mode, when a multiprocessor format is not used,  
and when the operation is not transmission.  
Unlike transmit data, the MPBT bit is not double-buffered, so it is necessary to check whether  
transmission has been completed before changing its value.  
Bit 0: MPBT  
Description  
0
1
Data with a 0 multiprocessor bit is transmitted  
Data with a 1 multiprocessor bit is transmitted  
(Initial value)  
Rev. 6.0, 07/02, page 608 of 986  
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