No function is assigned to bits 18 and 16 of the CHCR2–CHCR7 registers. Writing to these bits of
the CHCR2–CHCR7 registers is invalid. If, however, a value is written to these bits, it should
always be 0. These bits are always read as 0.
These registers are initialized to H'00000000 by a power-on or manual reset. Their values are
retained in standby, sleep, and deep-sleep modes.
Bits 31 to 29—Source Address Space Attribute Specification (SSA2–SSA0): These bits specify
the space attribute for PCMCIA access. These bits are only valid in the case of page mapping to
PCMCIA connected to areas 5 and 6. For details of the settings, see the description of the SSA2-
SSA0 bits in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3).
Bit 28—Source Address Wait Control Select (STC): Specifies CS5 or CS6 space wait control
for PCMCIA access. This bit selects the wait control register in the BSC that performs area 5 and
6 wait cycle control. For details of the settings, see the description of the STC bit in section 14.2.4,
DMA Channel Control Registers 0–3 (CHCR0–CHCR3).
Bits 27 to 25—Destination Address Space Attribute Specification (DSA2–DSA0): These bits
specify the space attribute for PCMCIA access. These bits are only valid in the case of page
mapping to PCMCIA connected to areas 5 and 6. For details of the settings, see the description of
the DSA2–DSA0 bits in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3).
Bit 24—Destination Address Wait Control Select (DTC): Specifies CS5 or CS6 space wait
cycle control for PCMCIA access. This bit selects the wait control register in the BSC that
performs area 5 and 6 wait cycle control. For details of the settings, see the description of the DTC
bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–CHCR3).
Bits 23 to 20—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 19—'5(4 Select (DS): Specifies either low level detection or falling edge detection as the
sampling method for the '5(4 pin used in external request mode.
In normal DMA mode, this bit is valid only in CHCR0 and CHCR1. In DDT mode, it is valid in
CHCR0–CHCR7. For details of the settings, see the description of the DS bit in section 14.2.4,
DMA Channel Control Registers 0–3 (CHCR0–CHCR3).
Bit 18—Request Check Level (RL): Selects whether the DRAK signal (that notifies an external
device of the acceptance of '5(4) is an active-high or active-low output.
This bit is valid only in CHCR0 and CHCR1 in normal mode, and is invalid in DDT mode. For
details of the settings, see the description of the RL bit in section 14.2.4, DMA Channel Control
Registers 0–3 (CHCR0–CHCR3).
Rev. 6.0, 07/02, page 581 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
