Table 14.13 Register Configuration
Chan-
nel
Abbre-
viation
Read/
Area 7
Access
Size
Name
Write Initial Value P4 Address Address
2
*
*
*
0
1
2
3
DMA source
address register 0
SAR0
R/W
R/W
Undefined H'FFA00000 H'1FA00000 32
2
2
DMA destination
address register 0
DAR0
Undefined H'FFA00004 H'1FA00004 32
Undefined H'FFA00008 H'1FA00008 32
H'00000000 H'FFA0000C H'1FA0000C 32
Undefined H'FFA00010 H'1FA00010 32
Undefined H'FFA00014 H'1FA00014 32
Undefined H'FFA00018 H'1FA00018 32
H'00000000 H'FFA0001C H'1FA0001C 32
Undefined H'FFA00020 H'1FA00020 32
Undefined H'FFA00024 H'1FA00024 32
Undefined H'FFA00028 H'1FA00028 32
H'00000000 H'FFA0002C H'1FA0002C 32
Undefined H'FFA00030 H'1FA00030 32
Undefined H'FFA00034 H'1FA00034 32
Undefined H'FFA00038 H'1FA00038 32
H'00000000 H'FFA0003C H'1FA0003C 32
H'00000000 H'FFA00040 H'1FA00040 32
DMA transfer
count register 0
DMATCR0 R/W
*1*2
DMA channel
control register 0
CHCR0
SAR1
R/W
R/W
R/W
DMA source
address register 1
DMA destination
address register 1
DAR1
DMA transfer
count register 1
DMATCR1 R/W
1
*
DMA channel
control register 1
CHCR1
SAR2
R/W
R/W
R/W
DMA source
address register 2
DMA destination
address register 2
DAR2
DMA transfer
count register 2
DMATCR2 R/W
1
*
DMA channel
control register 2
CHCR2
SAR3
R/W
R/W
R/W
DMA source
address register 3
DMA destination
address register 3
DAR3
DMA transfer
count register 3
DMATCR3 R/W
1
*
DMA channel
control register 3
CHCR3
DMAOR
R/W
R/W
1
*
Com- DMA operation
mon register
Rev. 6.0, 07/02, page 577 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
