CHCR Bit 3
QCL
Description
0
This bit is always read as 0.
Writing a 0 to this bit is invalid.
(Initial value)
1
When DMAOR.DBL = 1, writing a 1 to this bit clears the request queues on the
DDT side and any external requests stored in the DMAC. The written value is
not retained.
Bit 2—Interrupt Enable (IE): When this bit is set to 1, an interrupt request (DMTE) is generated
after the number of data transfers specified in DMATCR (when TE = 1). For details of the
settings, see the description of the IE bit in section 14.2.4, DMA Channel Control Registers 0–3
(CHCR0–CHCR3).
Bit 1—Transfer End (TE): This bit is set to 1 after the number of transfers specified in
DMATCR. If the IE bit is set to 1 at this time, an interrupt request (DMTE) is generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI interrupt, address error, or
clearing of the DE bit or the DME bit in DMAOR), the TE bit is not set to 1. When this bit is 1,
the transfer enabled state is not entered even if the DE bit is set to 1. For details of the settings, see
the description of the TE bit in section 14.2.4, DMA Channel Control Registers 0–3 (CHCR0–
CHCR3).
Bit 0—DMAC Enable (DE): Enables operation of the corresponding channel. For details of the
settings, see the description of the DE bit in section 14.2.4, DMA Channel Control Registers 0–3
(CHCR0–CHCR3).
14.7.5 DMA Operation Register (DMAOR)
Bit: 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15
14
13
—
0
12
—
0
11
—
0
10
—
0
9
8
7
—
0
6
—
0
5
—
0
4
—
0
3
—
0
2
1
0
DDT DBL
PR1 PR0
AE NMIF DME
Initial value:
0
0
0
0
0
0
0
R/W: R/W R/W
R
R
R
R
R/W R/W
R
R
R
R
R
R/(W)R/(W) R/W
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
Rev. 6.0, 07/02, page 583 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
