Table 14.13 Register Configuration (cont)
Chan-
nel
Abbre-
viation
Read/
Area 7
Access
Size
Name
Write Initial Value P4 Address Address
4
5
6
7
DMA source
address register 4
SAR4
R/W
R/W
Undefined H'FFA00050 H'1FA00050 32
DMA destination
address register 4
DAR4
Undefined H'FFA00054 H'1FA00054 32
Undefined H'FFA00058 H'1FA00058 32
H'00000000 H'FFA0005C H'1FA0005C 32
Undefined H'FFA00060 H'1FA00060 32
Undefined H'FFA00064 H'1FA00064 32
Undefined H'FFA00068 H'1FA00068 32
H'00000000 H'FFA0006C H'1FA0006C 32
Undefined H'FFA00070 H'1FA00070 32
Undefined H'FFA00074 H'1FA00074 32
Undefined H'FFA00078 H'1FA00078 32
H'00000000 H'FFA0007C H'1FA0007C 32
Undefined H'FFA00080 H'1FA00080 32
Undefined H'FFA00084 H'1FA00084 32
Undefined H'FFA00088 H'1FA00088 32
H'00000000 H'FFA0008C H'1FA0008C 32
DMA transfer
count register 4
DMATCR4 R/W
1
1
1
1
*
*
*
*
DMA channel
control register 4
CHCR4
SAR5
R/W
R/W
R/W
DMA source
address register 5
DMA destination
address register 5
DAR5
DMA transfer
count register 5
DMATCR5 R/W
DMA channel
control register 5
CHCR5
SAR6
R/W
R/W
R/W
DMA source
address register 6
DMA destination
address register 6
DAR6
DMA transfer
count register 6
DMATCR6 R/W
DMA channel
control register 6
CHCR6
SAR7
R/W
R/W
R/W
DMA source
address register 7
DMA destination
address register 7
DAR7
DMA transfer
count register 7
DMATCR7 R/W
CHCR7 R/W
DMA channel
control register 7
Notes: Longword access should be used for all control registers. If a different access width is
used, reads will return all 0s and writes will not be possible.
*1 Bit 1 of CHCR0–CHCR7 and bits 2 and 1 of DMAOR can only be written with 0 after
being read as 1, to clear the flags.
*2 In the SH7750R, writes from the CPU and writes from external I/O devices using the
DTR format are possible in DDT mode.
Rev. 6.0, 07/02, page 578 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
