Start
Initial settings
(SAR, DAR, DMATCR,
CHCR, DMAOR)
No
DE, DME = 1?
Yes
*4
Illegal address check
(reflected in AE bit)
No
No
NMIF, AE, TE = 0?
Yes
*2
Transfer
request issued?
*1
Bus mode,
transfer request mode,
detection
*3
Yes
method
Transfer (1 transfer unit)
DMATCR - 1
→ DMATCR
Update SAR, DAR
NMIF or
AE = 1 or DE = 0 or
DME = 0?
No
No
DMATCR = 0?
Yes
Yes
DMTE interrupt request
(when IE = 1)
Transfer suspended
NMIF or
AE = 1 or DE = 0 or
DME = 0?
No
Yes
End of transfer
Normal end
Notes: *1 In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0, and the DE
and DME bits are set to 1.
*2
*3
level detection (external request) in burst mode, or cycle steal mode.
edge detection (external request) in burst mode, or auto-request mode in burst mode.
*4 An illegal address is detected by comparing bits TS2–TS0 in CHCRn with SARn and DARn.
Figure 14.2 DMAC Transfer Flowchart
Rev. 6.0, 07/02, page 511 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
