Burst Write: The timing chart for a burst write is shown in figure 13.30. In the SH7750 Series, a
burst write occurs only in the event of cache copy-back or a 32-byte transfer by the DMAC. In a
burst write operation, the WRITA command is issued in the Tc1 cycle following the Tr cycle in
which the ACTV command is output. In the write cycle, the write data is output at the same time
as the write command. In the case of the write with auto-precharge command, precharging of the
relevant bank is performed in the synchronous DRAM after completion of the write command,
and therefore no command can be issued for the same bank until precharging is completed.
Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is
also added as a wait interval until precharging is started following the write command. Issuance of
a new command for synchronous DRAM is postponed during this interval. The number of Trwl
cycles can be specified by bits TRWL2–TRWL0 in MCR. 32-byte boundary data is written in
wraparound mode. DACK is asserted two cycles before the data write cycle.
Tr
Trw
Tc1
Tc2
Tc3
Tc4
Trw1
Trw1
Tpc
CKIO
Bank
Row
Precharge-sel
Address
Row
Row
H/L
c1
RD/
DQMn
D63–D0
(read)
c1
c2
c3
c4
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.30 Basic Timing for Synchronous DRAM Burst Write
Rev. 6.0, 07/02, page 419 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
