Figure 21.3
Figure 22.1
H-UDI Reset..................................................................................................... 811
EXTAL Clock Input Timing ............................................................................ 862
Figure 22.2(1) CKIO Clock Output Timing............................................................................. 862
Figure 22.2(2) CKIO Clock Output Timing............................................................................. 862
Figure 22.3
Figure 22.4
Figure 22.5
Figure 22.6
Figure 22.7
Figure 22.8
Figure 22.9
Figure 22.10
Figure 22.11
Figure 22.12
Figure 22.13
Figure 22.14
Figure 22.15
Figure 22.16
Figure 22.17
Figure 22.18
Power-On Oscillation Settling Time ................................................................ 863
Standby Return Oscillation Settling Time (Return by 5(6(7) ....................... 863
Power-On Oscillation Settling Time ................................................................ 864
Standby Return Oscillation Settling Time (Return by 5(6(7) ....................... 864
Standby Return Oscillation Settling Time (Return by NMI)............................ 865
Standby Return Oscillation Settling Time (Return by ,5/6–,5/3)................. 865
PLL Synchronization Settling Time in Case of 5(6(7 or NMI Interrupt....... 866
PLL Synchronization Settling Time in Case of IRL Interrupt.......................... 866
Manual Reset Input Timing.............................................................................. 867
Mode Input Timing .......................................................................................... 867
Control Signal Timing...................................................................................... 870
Pin Drive Timing for Standby Mode................................................................ 870
SRAM Bus Cycle: Basic Bus Cycle (No Wait)................................................ 877
SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait) ................................ 878
SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait + One External Wait)879
SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time
Insertion, AnS = 1, AnH = 1)........................................................................... 880
Burst ROM Bus Cycle (No Wait) .................................................................... 881
Burst ROM Bus Cycle (1st Data: One Internal Wait + One External Wait;
2nd/3rd/4th Data: One Internal Wait)............................................................... 882
Burst ROM Bus Cycle (No Wait, Address Setup/Hold Time Insertion,
AnS = 1, AnH = 1) ........................................................................................... 883
Burst ROM Bus Cycle (One Internal Wait + One External Wait) ................... 884
Synchronous DRAM Auto-Precharge Read Bus Cycle:
Figure 22.19
Figure 22.20
Figure 22.21
Figure 22.22
Figure 22.23
Single (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011)........................... 885
Synchronous DRAM Auto-Precharge Read Bus Cycle:
Burst (RCD[1:0] = 01, CAS Latency = 3, TPC[2:0] = 011) ............................ 886
Synchronous DRAM Normal Read Bus Cycle:
ACT + READ Commands, Burst (RCD[1:0] = 01, CAS Latency = 3)............ 887
Synchronous DRAM Normal Read Bus Cycle:
Figure 22.24
Figure 22.25
Figure 22.26
PRE + ACT + READ Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001,
CAS Latency = 3)............................................................................................. 888
Synchronous DRAM Normal Read Bus Cycle:
READ Command, Burst (CAS Latency = 3) ................................................... 889
Synchronous DRAM Auto-Precharge Write Bus Cycle:
Figure 22.27
Figure 22.28
Figure 22.29
Single (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010).......................... 890
Synchronous DRAM Auto-Precharge Write Bus Cycle:
Burst (RCD[1:0] = 01, TPC[2:0] = 001, TRWL[2:0] = 010)........................... 891
Rev. 6.0, 07/02, page xliii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
