Table 7.12
Table 8.1
Table 8.2
Table 8.3
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 10.1
Table 10.2
Floating-Point Graphics Acceleration Instructions ............................................ 191
Instruction Groups.............................................................................................. 200
Parallel-Executability......................................................................................... 204
Execution Cycles................................................................................................ 211
Status of CPU and Peripheral Modules in Power-Down Modes........................ 222
Power-Down Mode Registers ............................................................................ 223
Power-Down Mode Pins .................................................................................... 223
State of Registers in Standby Mode ................................................................... 231
CPG Pins............................................................................................................ 252
CPG Register...................................................................................................... 252
Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S).................................................... 253
Table 10.3 (2) Clock Operating Modes (SH7750R) .................................................................. 253
Table 10.4
Table 10.5
Table 11.1
Table 11.2
Table 11.3
Table 12.1
Table 12.2
Table 12.3
Table 13.1
Table 13.2
Table 13.3
Table 13.4
Table 13.5
Table 13.6
FRQCR Settings and Internal Clock Frequencies.............................................. 254
WDT Registers................................................................................................... 260
RTC Pins............................................................................................................ 269
RTC Registers .................................................................................................... 269
Crystal Oscillator Circuit Constants (Recommended Values) ........................... 289
TMU Pins........................................................................................................... 292
TMU Registers................................................................................................... 293
TMU Interrupt Sources ...................................................................................... 309
BSC Pins ............................................................................................................ 314
BSC Registers .................................................................................................... 318
External Memory Space Map............................................................................. 320
PCMCIA Interface Features............................................................................... 322
PCMCIA Support Interfaces .............................................................................. 323
MPX Interface is Selected (Areas 0 to 6)........................................................... 350
Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment...................... 372
Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment...................... 373
Table 13.8
Table 13.9
Table 13.10
32-Bit External Device/Big-Endian Access and Data Alignment...................... 374
16-Bit External Device/Big-Endian Access and Data Alignment...................... 375
8-Bit External Device/Big-Endian Access and Data Alignment........................ 376
Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment................... 377
Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment................... 378
Table 13.12
Table 13.13
Table 13.14
Table 13.15
32-Bit External Device/Little-Endian Access and Data Alignment................... 379
16-Bit External Device/Little-Endian Access and Data Alignment................... 380
8-Bit External Device/Little-Endian Access and Data Alignment..................... 381
Relationship between AMXEXT and AMX2–0 Bits and
Address Multiplexing......................................................................................... 399
Example of Correspondence between SH7750 Series and Synchronous DRAM
Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0)......... 416
Cycles for which Pipeline Access is Possible .................................................... 431
Relationship between Address and CE when Using PCMCIA Interface ........... 446
DMAC Pins........................................................................................................ 493
Table 13.16
Table 13.17
Table 13.18
Table 14.1
Rev. 6.0, 07/02, page xlvii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
