Figure 22.30
Figure 22.31
Synchronous DRAM Normal Write Bus Cycle:
ACT + WRITE Commands, Burst (RCD[1:0] = 01, TRWL[2:0] = 010) ........ 892
Synchronous DRAM Normal Write Bus Cycle:
PRE + ACT + WRITE Commands, Burst (RCD[1:0] = 01, TPC[2:0] = 001,
TRWL[2:0] = 010) ........................................................................................... 893
Synchronous DRAM Normal Write Bus Cycle:
WRITE Command, Burst (TRWL[2:0] = 010) ................................................ 894
Synchronous DRAM Bus Cycle:
Synchronous DRAM Precharge Command (TPC[2:0] = 001)......................... 895
Synchronous DRAM Bus Cycle:
Synchronous DRAM Auto-Refresh (TRAS = 1, TRC[2:0] = 001).................. 896
Synchronous DRAM Bus Cycle:
Figure 22.32
Figure 22.33
Figure 22.34
Figure 22.35
Synchronous DRAM Self-Refresh (TRC[2:0] = 001)...................................... 897
Figure 22.36 (a) Synchronous DRAM Bus Cycle:
Synchronous DRAM Mode Register Setting (PALL)...................................... 898
Figure 22.36 (b) Synchronous DRAM Bus Cycle:
Synchronous DRAM Mode Register Setting (SET)......................................... 899
DRAM Bus Cycles
Figure 22.37
(1) RCD[1:0] = 00, AnW[2:0] = 000, TPC[2:0] = 001
(2) RCD[1:0] = 01, AnW[2:0] = 001, TPC[2:0] = 010 .................................... 900
DRAM Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000,
TPC[2:0] = 001) ............................................................................................... 901
DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 00, AnW[2:0] = 000,
TPC[2:0] = 001) ............................................................................................... 902
DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001,
TPC[2:0] = 001) ............................................................................................... 903
DRAM Burst Bus Cycle (EDO Mode, RCD[1:0] = 01, AnW[2:0] = 001,
TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width) ....................................... 904
DRAM Burst Bus Cycle: RAS Down Mode State (EDO Mode,
RCD[1:0] = 00, AnW[2:0] = 000).................................................................... 905
DRAM Burst Bus Cycle: RAS Down Mode Continuation (EDO Mode,
RCD[1:0] = 00, AnW[2:0] = 000).................................................................... 906
DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 00,
AnW[2:0] = 000, TPC[2:0] = 001)................................................................... 907
DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01,
Figure 22.38
Figure 22.39
Figure 22.40
Figure 22.41
Figure 22.42
Figure 22.43
Figure 22.44
Figure 22.45
Figure 22.46
Figure 22.47
Figure 22.48
AnW[2:0] = 001, TPC[2:0] = 001)................................................................... 908
DRAM Burst Bus Cycle (Fast Page Mode, RCD[1:0] = 01,
AnW[2:0] = 001, TPC[2:0] = 001, 2-Cycle CAS Negate Pulse Width)........... 909
DRAM Burst Bus Cycle: RAS Down Mode State (Fast Page Mode,
RCD[1:0] = 00, AnW[2:0] = 000).................................................................... 910
DRAM Burst Bus Cycle: RAS Down Mode Continuation
(Fast Page Mode, RCD[1:0] = 00, AnW[2:0] = 000)....................................... 911
Rev. 6.0, 07/02, page xliv of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
