Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
Figure 14.5
Figure 14.6
Figure 14.7
Figure 14.8
Figure 14.9
Figure 14.10
Figure 14.11
Figure 14.12
Block Diagram of DMAC................................................................................ 492
DMAC Transfer Flowchart .............................................................................. 511
Round Robin Mode.......................................................................................... 516
Example of Changes in Priority Order in Round Robin Mode......................... 517
Data Flow in Single Address Mode.................................................................. 519
DMA Transfer Timing in Single Address Mode.............................................. 520
Operation in Dual Address Mode..................................................................... 521
Example of Transfer Timing in Dual Address Mode....................................... 522
Example of DMA Transfer in Cycle Steal Mode............................................. 523
Example of DMA Transfer in Burst Mode....................................................... 523
Bus Handling with Two DMAC Channels Operating...................................... 527
Dual Address Mode/Cycle Steal Mode External Bus External Bus/
→
'5(4 (Level Detection), DACK (Read Cycle)............................................... 530
Figure 14.13
Figure 14.14
Figure 14.15
Figure 14.16
Figure 14.17
Figure 14.18
Figure 14.19
Figure 14.20
Figure 14.21
Figure 14.22
Dual Address Mode/Cycle Steal Mode External Bus External Bus/
→
'5(4 (Edge Detection), DACK (Read Cycle) ............................................... 531
Dual Address Mode/Burst Mode External Bus External Bus/
→
'5(4 (Level Detection), DACK (Read Cycle)............................................... 532
Dual Address Mode/Burst Mode External Bus External Bus/
→
'5(4 (Edge Detection), DACK (Read Cycle) ............................................... 533
Dual Address Mode/Cycle Steal Mode On-Chip SCI (Level Detection)
→
External Bus..................................................................................................... 534
Dual Address Mode/Cycle Steal Mode External Bus On-Chip SCI
→
(Level Detection).............................................................................................. 535
Single Address Mode/Cycle Steal Mode External Bus External Bus/
→
'5(4 (Level Detection).................................................................................. 536
Single Address Mode/Cycle Steal Mode External Bus External Bus/
→
'5(4 (Edge Detection)................................................................................... 537
Single Address Mode/Burst Mode External Bus
External Bus/
→
'5(4 (Level Detection).................................................................................. 538
Single Address Mode/Burst Mode External Bus External Bus/
→
'5(4 (Edge Detection)................................................................................... 539
Single Address Mode/Burst Mode External Bus External Bus/
→
'5(4 (Level Detection)/32-Byte Block Transfer
(Bus Width: 64 Bits, SDRAM: Row Hit Write)............................................... 540
On-Demand Transfer Mode Block Diagram.................................................... 545
System Configuration in On-Demand Data Transfer Mode............................. 547
Data Transfer Request Format ......................................................................... 548
Figure 14.23
Figure 14.24
Figure 14.25
Figure 14.26
Single Address Mode: Synchronous DRAM External Device Longword
→
Transfer SDRAM auto-precharge Read bus cycle, burst (RCD[1:0] = 01,
CAS latency = 3, TPC[2:0] = 001)....................................................................... 551
Figure 14.27
Single Address Mode: External Device Synchronous DRAM Longword
→
Transfer SDRAM auto-precharge Write bus cycle, burst (RCD[1:0] = 01,
TRWL[2:0] = 101, TPC[2:0] = 001).................................................................... 552
Rev. 6.0, 07/02, page xxxix of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
