Figure 14.28
Figure 14.29
Dual Address Mode/Synchronous DRAM
Single Address Mode/Burst Mode/External Bus
SRAM Longword Transfer...... 553
→
External Device 32-Byte
→
Block Transfer/Channel 0 On-Demand Data Transfer..................................... 554
Single Address Mode/Burst Mode/External Device External Bus 32-Byte
Figure 14.30
Figure 14.31
Figure 14.32
→
Block Transfer/Channel 0 On-Demand Data Transfer..................................... 554
Single Address Mode/Burst Mode/External Bus External Device 32-Bit
→
Transfer/Channel 0 On-Demand Data Transfer ............................................... 555
Single Address Mode/Burst Mode/External Device External Bus 32-Bit
→
Transfer/Channel 0 On-Demand Data Transfer ............................................... 556
Handshake Protocol Using Data Bus (Channel 0 On-Demand Data Transfer) 557
Handshake Protocol without Use of Data Bus (Channel 0 On-Demand Data
Transfer)........................................................................................................... 558
Read from Synchronous DRAM Precharge Bank............................................ 559
Read from Synchronous DRAM Non-Precharge Bank (Row Miss)................ 559
Read from Synchronous DRAM (Row Hit)..................................................... 560
Write to Synchronous DRAM Precharge Bank................................................ 560
Write to Synchronous DRAM Non-Precharge Bank (Row Miss).................... 561
Write to Synchronous DRAM (Row Hit)......................................................... 561
Figure 14.33
Figure 14.34
Figure 14.35
Figure 14.36
Figure 14.37
Figure 14.38
Figure 14.39
Figure 14.40
Figure 14.41
Single Address Mode/Burst Mode/External Bus
External Device 32-Byte
→
Block Transfer/Channel 0 On-Demand Data Transfer..................................... 562
DDT Mode Setting........................................................................................... 563
Figure 14.42
Figure 14.43
Single Address Mode/Burst Mode/Edge Detection/ External Device
→
External Bus Data Transfer.............................................................................. 563
Single Address Mode/Burst Mode/Level Detection/ External Bus
External Device Data Transfer......................................................................... 564
Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Figure 14.44
Figure 14.45
Figure 14.46
Figure 14.47
Figure 14.48
→
Quadword/External Bus
External Device Data Transfer............................. 564
→
Single Address Mode/Burst Mode/Edge Detection/Byte, Word, Longword,
Quadword/External Device External Bus Data Transfer............................. 565
→
Single Address Mode/Burst Mode/32-Byte Block Transfer/DMA Transfer
Request to Channels 1–3 Using Data Bus........................................................ 566
Single Address Mode/Burst Mode/32-Byte Block Transfer/ External Bus
→
External Device Data Transfer/ Direct Data Transfer Request to Channel 2
without Using Data Bus ................................................................................... 567
Figure 14.49
Figure 14.50
Figure 14.51
Figure 14.52
Figure 14.53
Single Address Mode/Burst Mode/External Bus
Transfer/Direct Data Transfer Request to Channel 2 ....................................... 568
Single Address Mode/Burst Mode/External Device External Bus Data
Transfer/Direct Data Transfer Request to Channel 2 ....................................... 569
Single Address Mode/Burst Mode/External Bus External Device Data
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 570
Single Address Mode/Burst Mode/External Device External Bus Data
External Device Data
→
→
→
→
Transfer (Active Bank Address)/Direct Data Transfer Request to Channel 2.. 571
Block Diagram of the DMAC .......................................................................... 574
Rev. 6.0, 07/02, page xl of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
