LMODE: RAS-CAS latency
BL:
Burst length
WT:
Wrap type (0: Sequential)
BL
LMODE
000: Reserved
001: Reserved
010: 4
000: Reserved
001: 1
010: 2
011: 8
011: 3
100: Reserved
101: Reserved
110: Reserved
111: Reserved
100: Reserved
101: Reserved
110: Reserved
111: Reserved
Note: * SH7750R only.
13.2.11 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that
specifies the refresh cycle and whether interrupts are to be generated.
RTCSR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit:
Bit name:
Initial value:
R/W:
15
—
0
14
—
0
13
—
0
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
—
—
—
—
—
—
—
—
Bit:
Bit name:
Initial value:
R/W:
7
6
CMIE
0
5
CKS2
0
4
CKS1
0
3
CKS0
0
2
1
OVIE
0
0
LMTS
0
CMF
0
OVF
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 15 to 8—Reserved: These bits are always read as 0. For the write values, see section 13.2.15,
Notes on Accessing Refresh Control Registers.
Rev. 6.0, 07/02, page 364 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
