13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only)
Bus control register 3 (BCR3) is a 16-bit readable/writable register that specifies the selection of
either the MPX interface or the SRAM interface and specifies the burst length when the
synchronous DRAM interface is used.
BCR3 is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. No external memory space other than area 0 should be accessed before register
initialization has been completed.
Bit:
15
14
13
12
—
0
11
—
0
10
—
0
9
—
0
8
—
0
Bit name: MEMMODE A1MPX A4MPX
Initial value:
R/W:
0
0
0
R/W
R/W
R/W
R
R
R
R
R
Bit:
Bit name:
Initial value:
R/W:
7
—
0
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
SDBL
0
R
R
R
R
R
R
R
R/W
Bit 15 A1MPX/A4MPX Enable (MEMMODE): Determines whether or not the selection of
either the MPX interface or the SRAM interface is by A1MPX and A4MPX rather than by
MEMMPX.
Bit 15: MEMMODE Description
0
1
MPX or SRAM interface is selected by MEMMPX
(Initial value)
MPX or SRAM interface is selected by A1MPX and A4MPX
Bits 14 and 13 MPX-Interface Specification for Area 1 and 4 (A1MPX, A4MPX): These
bits specify the types of memory connected to areas 1 and 4. These settings are validated by
MEMMODE.
Bit 14: A1MPX
Description
0
1
SRAM/byte control SRAM interface is selected for area 1
MPX interface is selected for area 1
(Initial value)
Bit 13: A4MPX
Description
0
1
SRAM/byte control SRAM interface is selected for area 4
MPX interface is selected for area 4
(Initial value)
Rev. 6.0, 07/02, page 337 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
