Figure 13.26
Figure 13.27
Figure 13.28
Figure 13.29
Figure 13.30
Figure 13.31
Figure 13.32
Figure 13.33
Figure 13.34
Figure 13.35
Figure 13.36
Figure 13.37
Figure 13.38
Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) .... 414
Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .... 415
Basic Timing for Synchronous DRAM Burst Read ......................................... 417
Basic Timing for Synchronous DRAM Single Read........................................ 418
Basic Timing for Synchronous DRAM Burst Write ........................................ 419
Basic Timing for Synchronous DRAM Single Write....................................... 421
Burst Read Timing ........................................................................................... 423
Burst Read Timing (RAS Down, Same Row Address).................................... 424
Burst Read Timing (RAS Down, Different Row Addresses)........................... 425
Burst Write Timing .......................................................................................... 426
Burst Write Timing (Same Row Address) ....................................................... 427
Burst Write Timing (Different Row Addresses) .............................................. 428
Burst Read Cycle for Different Bank and Row Address Following
Preceding Burst Read Cycle............................................................................. 430
Auto-Refresh Operation ................................................................................... 432
Synchronous DRAM Auto-Refresh Timing..................................................... 432
Synchronous DRAM Self-Refresh Timing ...................................................... 434
Figure 13.39
Figure 13.40
Figure 13.41
Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) ......................................... 436
Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set)...................... 437
Figure 13.43
Figure 13.44
Figure 13.45
Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4)............ 438
Basic Timing of a Burst Write to Synchronous DRAM................................... 440
Example of the Connection of Synchronous DRAM with 64-bit Bus Width
(256 Mbits)....................................................................................................... 441
Burst ROM Basic Access Timing .................................................................... 442
Burst ROM Wait Access Timing ..................................................................... 443
Burst ROM Wait Access Timing ..................................................................... 444
Example of PCMCIA Interface........................................................................ 448
Basic Timing for PCMCIA Memory Card Interface........................................ 449
Wait Timing for PCMCIA Memory Card Interface......................................... 450
PCMCIA Space Allocation .............................................................................. 451
Basic Timing for PCMCIA I/O Card Interface ................................................ 452
Wait Timing for PCMCIA I/O Card Interface ................................................. 453
Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ........................ 454
Example of 64-Bit Data Width MPX Connection............................................ 456
MPX Interface Timing 1
Figure 13.46
Figure 13.47
Figure 13.48
Figure 13.49
Figure 13.50
Figure 13.51
Figure 13.52
Figure 13.53
Figure 13.54
Figure 13.55
Figure 13.56
Figure 13.57
(Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits) .......... 457
MPX Interface Timing 2
(Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits)..... 458
MPX Interface Timing 3
(Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits)........................ 459
MPX Interface Timing 4
Figure 13.58
Figure 13.59
Figure 13.60
(Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits).... 460
Rev. 6.0, 07/02, page xxxvii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
