Figure 4.8
Figure 4.9
Figure 4.10
Figure 4.11
Figure 4.12
Figure 4.13
Figure 4.14
Figure 4.15
Figure 4.16
Figure 5.1
Figure 5.2
Figure 5.3
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 8.1
Figure 8.2
Figure 8.3
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Figure 9.10
Figure 9.11
Figure 9.12
Figure 9.13
Figure 9.14
Figure 9.15
Memory-Mapped IC Address Array ................................................................ 113
Memory-Mapped IC Data Array...................................................................... 114
Memory-Mapped OC Address Array............................................................... 115
Memory-Mapped OC Data Array .................................................................... 116
Memory-Mapped IC Address Array ................................................................ 118
Memory-Mapped IC Data Array...................................................................... 119
Memory-Mapped OC Address Array............................................................... 120
Memory-Mapped OC Data Array .................................................................... 121
Store Queue Configuration............................................................................... 122
Register Bit Configurations.............................................................................. 128
Instruction Execution and Exception Handling................................................ 133
Example of General Exception Acceptance Order........................................... 134
Format of Single-Precision Floating-Point Number......................................... 161
Format of Double-Precision Floating-Point Number ....................................... 162
Single-Precision NaN Bit Pattern..................................................................... 164
Floating-Point Registers................................................................................... 166
Basic Pipelines ................................................................................................. 194
Instruction Execution Patterns.......................................................................... 195
Examples of Pipelined Execution..................................................................... 207
STATUS Output in Power-On Reset ............................................................... 237
STATUS Output in Manual Reset.................................................................... 237
STATUS Output in Standby
STATUS Output in Standby
STATUS Output in Standby
Interrupt Sequence......................................... 238
Power-On Reset Sequence ............................ 238
Manual Reset Sequence................................. 239
→
→
→
STATUS Output in Sleep Interrupt Sequence............................................. 240
→
STATUS Output in Sleep Power-On Reset Sequence................................. 240
→
STATUS Output in Sleep Manual Reset Sequence..................................... 241
→
STATUS Output in Deep Sleep Interrupt Sequence ................................... 242
→
STATUS Output in Deep Sleep
STATUS Output in Deep Sleep
Power-On Reset Sequence ....................... 242
Manual Reset Sequence ........................... 243
→
→
Hardware Standby Mode Timing (When CA = Low in Normal Operation).... 244
Hardware Standby Mode Timing (When CA = Low in WDT Operation)....... 245
Timing When Power Other than VDD-RTC is Off.......................................... 246
Timing When VDD-RTC Power is Off On................................................. 246
→
Figure 10.1 (1) Block Diagram of CPG (SH7750, SH7750S) .................................................. 249
Figure 10.1 (2) Block Diagram of CPG (SH7750R)................................................................. 250
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 11.1
Figure 11.2
Figure 11.3
Block Diagram of WDT................................................................................... 259
Writing to WTCNT and WTCSR..................................................................... 263
Points for Attention when Using Crystal Resonator......................................... 265
Points for Attention when Using PLL Oscillator Circuit ................................. 266
Block Diagram of RTC .................................................................................... 268
Examples of Time Setting Procedures ............................................................. 285
Examples of Time Reading Procedures ........................................................... 287
Rev. 6.0, 07/02, page xxxv of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
