Figure 11.4
Figure 11.5
Figure 12.1
Figure 12.2
Figure 12.3
Figure 12.4
Figure 12.5
Figure 12.6
Figure 12.7
Figure 13.1
Figure 13.2
Example of Use of Alarm Function.................................................................. 288
Example of Crystal Oscillator Circuit Connection........................................... 290
Block Diagram of TMU ................................................................................... 292
Example of Count Operation Setting Procedure .............................................. 305
TCNT Auto-Reload Operation......................................................................... 305
Count Timing when Operating on Internal Clock............................................ 306
Count Timing when Operating on External Clock........................................... 306
Count Timing when Operating on On-Chip RTC Output Clock...................... 307
Operation Timing when Using Input Capture Function................................... 308
Block Diagram of BSC..................................................................................... 313
Correspondence between Virtual Address Space and External Memory
Space ................................................................................................................ 319
External Memory Space Allocation ................................................................. 321
Example of 5'< Sampling Timing at which BCR4 is Set
Figure 13.3
Figure 13.4
(Two Wait Cycles are Inserted by WCR2)....................................................... 338
Writing to RTCSR, RTCNT, RTCOR, and RFCR........................................... 370
Basic Timing of SRAM Interface..................................................................... 388
Example of 64-Bit Data Width SRAM Connection ......................................... 389
Example of 32-Bit Data Width SRAM Connection ......................................... 390
Example of 16-Bit Data Width SRAM Connection ......................................... 391
Example of 8-Bit Data Width SRAM Connection ........................................... 392
SRAM Interface Wait Timing (Software Wait Only) ...................................... 393
SRAM Interface Wait State Timing (Wait State Insertion by 5'< Signal) .... 394
SRAM Interface Read-Strobe Negate Timing (AnS = 1, AnW = 4, AnH = 2) 395
Example of DRAM Connection (64-Bit Data Width, Area 3) ......................... 396
Example of DRAM Connection (32-Bit Data Width, Area 3) ......................... 397
Example of DRAM Connection (16-Bit Data Width, Areas 2 and 3).............. 398
Basic DRAM Access Timing........................................................................... 400
DRAM Wait State Timing ............................................................................... 401
DRAM Burst Access Timing ........................................................................... 402
DRAM Bus Cycle (EDO Mode, RCD = 0, AnW = 0, TPC = 1)...................... 403
Burst Access Timing in DRAM EDO Mode.................................................... 404
Figure 13.5
Figure 13.6
Figure 13.7
Figure 13.8
Figure 13.9
Figure 13.10
Figure 13.11
Figure 13.12
Figure 13.13
Figure 13.14
Figure 13.15
Figure 13.16
Figure 13.17
Figure 13.18
Figure 13.19
Figure 13.20
Figure 13.21
Figure 13.22 (1) DRAM Burst Bus Cycle, RAS Down Mode Start
(Fast Page Mode, RCD = 0, AnW = 0) ............................................................ 405
Figure 13.22 (2) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(Fast Page Mode, RCD = 0, AnW = 0) ............................................................ 406
Figure 13.22 (3) DRAM Burst Bus Cycle, RAS Down Mode Start
(EDO Mode, RCD = 0, AnW = 0) ................................................................... 407
Figure 13.22 (4) DRAM Burst Bus Cycle, RAS Down Mode Continuation
(EDO Mode, RCD = 0, AnW = 0) ................................................................... 408
Figure 13.23
Figure 13.24
Figure 13.25
CAS-Before-RAS Refresh Operation............................................................... 409
DRAM CAS-Before-RAS Refresh Cycle Timing (TRAS = 0, TRC = 1)........ 410
DRAM Self-Refresh Cycle Timing.................................................................. 412
Rev. 6.0, 07/02, page xxxvi of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
