Appendix H Power-On and Power-Off Procedures................................................... 978
Appendix I Product Code Lineup ................................................................................. 979
Index........................................................................................................................................... 981
Figures
Figure 1.1
Figure 1.2
Figure 1.3
Figure 1.4
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 3.5
Figure 3.6
Figure 3.7
Figure 3.8
Figure 3.9
Figure 3.10
Figure 3.11
Figure 3.12
Figure 3.13
Figure 3.14
Figure 3.15
Figure 3.16
Figure 3.17
Figure 3.18
Figure 4.1
Figure 4.2
Figure 4.3
Figure 4.4
Figure 4.5
Figure 4.6
Figure 4.7
Block Diagram of SH7750 Series Functions....................................................
9
Pin Arrangement (256-Pin BGA)..................................................................... 10
Pin Arrangement (208-Pin QFP)...................................................................... 11
Pin Arrangement (264-Pin CSP) ...................................................................... 12
Data Formats .................................................................................................... 41
CPU Register Configuration in Each Processor Mode..................................... 44
General Registers ............................................................................................. 46
Floating-Point Registers................................................................................... 48
Data Formats In Memory ................................................................................. 53
Processor State Transitions .............................................................................. 55
Role of the MMU............................................................................................. 59
MMU-Related Registers................................................................................... 61
Physical Address Space (MMUCR.AT = 0) .................................................... 65
P4 Area............................................................................................................. 66
External Memory Space................................................................................... 67
Virtual Address Space (MMUCR.AT = 1)....................................................... 68
UTLB Configuration........................................................................................ 71
Relationship between Page Size and Address Format...................................... 72
ITLB Configuration.......................................................................................... 75
Flowchart of Memory Access Using UTLB..................................................... 76
Flowchart of Memory Access Using ITLB...................................................... 77
Operation of LDTLB Instruction ..................................................................... 79
Memory-Mapped ITLB Address Array............................................................ 88
Memory-Mapped ITLB Data Array 1 .............................................................. 89
Memory-Mapped ITLB Data Array 2 .............................................................. 90
Memory-Mapped UTLB Address Array.......................................................... 91
Memory-Mapped UTLB Data Array 1............................................................. 92
Memory-Mapped UTLB Data Array 2............................................................. 93
Cache and Store Queue Control Registers ....................................................... 97
Configuration of Operand Cache(SH7750, SH7750S)..................................... 100
Configuration of Operand Cache (SH7750R) .................................................. 101
Configuration of Write-Back Buffer ................................................................ 105
Configuration of Write-Through Buffer........................................................... 105
Configuration of Instruction Cache (SH7750, SH7750S)................................ 109
Configuration of Instruction Cache (SH7750R)............................................... 110
Rev. 6.0, 07/02, page xxxiv of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
