Table 13.1 BSC Pins (cont)
Name
Signals
I/O
Description
Data enable 6
:(9/&$69/
O
When setting synchronous DRAM interface:
selection signal for D55–D48
DQM6
When setting DRAM interface: &$6 signal for
D55–D48
When setting MPX interface: high-level output
In other cases: write strobe signal for D55–D48
Data enable 7
:(:/&$6:/
DQM7/5(*
O
When setting synchronous DRAM interface:
selection signal for D63–D56
When setting DRAM interface: &$6 signal for
D63–D56
When setting PCMCIA interface: 5(* signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D63–D56
Wait state request signal
Ready
5'<
MD6/,2,649
I
I
Area 0 MPX
interface
In power-on reset: Designates area 0 bus as MPX
interface (1: SRAM, 0: MPX)
specification/
16-bit I/O
When setting PCMCIA interface: 16-bit I/O
designation signal. Valid only in little-endian mode.
Clock enable
CKE
O
I
Synchronous DRAM clock enable control signal
Bus release request signal/bus acknowledge signal
Bus release
request
%5(4/
%6$&.
Bus use
permission
%$&./
O
Bus use permission signal/bus request
%65(4
1
2
4
*
*
Area 0 bus
width/PCMCIA
card select
MD3/&(5$
MD4/&(5%
I/O
In power-on reset : external space area 0 bus width
specification signal
*
When setting PCMCIA interface: &(5$, &(5%
Endian specification in a power-on reset.
3
4
*
*
Endian switchover/ MD5/5$65
I/O
I/O
O
row address strobe
5$65 when DRAM is connected to area 2
Indicates master/slave status in a power-on reset.
4
*
Master/slave
switchover
MD7/TXD
DACK0
Serial interface TXD
DMAC0
DMAC channel 0 data acknowledge
acknowledge
signal
DMAC1
DACK1
O
DMAC channel 1 data acknowledge
acknowledge
signal
Rev. 6.0, 07/02, page 316 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
