Table 13.1 BSC Pins (cont)
Name
Signals
I/O
Description
Data enable 1
:(4/&$64/
O
When setting synchronous DRAM interface:
selection signal for D15–D8
DQM1
When setting DRAM interface: &$6 signal for
D15–D8
When setting PCMCIA interface: write strobe signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D15–D8
Data enable 2
:(5/&$65/
O
When setting synchronous DRAM interface:
selection signal for D23–D16
DQM2/,&,25'
When setting DRAM interface: &$6 signal for
D23–D16
When setting PCMCIA interface: ,&,25' signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D23–D16
Data enable 3
:(6/&$66/
O
When setting synchronous DRAM interface:
selection signal for D31–D24
DQM3/,&,2:5
When setting DRAM interface: &$6 signal for
D31–D24
When setting PCMCIA interface: ,&,2:5 signal
When setting MPX interface: high-level output
In other cases: write strobe signal for D31–D24
Data enable 4
:(7/&$67/
O
O
When setting synchronous DRAM interface:
selection signal for D39–D32
DQM4
When setting DRAM interface: &$6 signal for
D39–D32
When setting MPX interface: high-level output
In other cases: write strobe signal for D39–D32
Data enable 5
:(8/&$68/
When setting synchronous DRAM interface:
selection signal for D47–D40
DQM5
When setting DRAM interface: &$6 signal for
D47–D40
When setting MPX interface: high-level output
In other cases: write strobe signal for D47–D40
Rev. 6.0, 07/02, page 315 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
