Consecutive accesses to the same row address
Connectable areas: 2, 3
Settable bus widths: 64, 32, 16
•
Synchronous DRAM interface
Row address/column address multiplexing according to synchronous DRAM capacity
Burst operation
Auto-refresh and self-refresh
Synchronous DRAM control signal timing can be controlled by register settings
Consecutive accesses to the same row address
Connectable areas: 2, 3
Settable bus widths: 64, 32
•
Burst ROM interface
Wait state insertion can be controlled by program
Burst operation, executing the number of transfers set in a register
Connectable areas: 0, 5, 6
Settable bus widths: 64*, 32, 16, 8
MPX interface
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•
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Address/data multiplexing
Connectable areas: 0 to 6
Settable bus widths: 64, 32
Byte control SRAM interface
SRAM interface with byte control
Connectable areas: 1, 4
Settable bus widths: 64, 32, 16
PCMCIA interface
Wait state insertion can be controlled by program
Bus sizing function for I/O bus width
Fine refreshing control
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•
Supports refresh operation immediately after self-refresh operation in low-power DRAM
by means of refresh counter overflow interrupt function
Refresh counter can be used as interval timer
Interrupt request generated by compare-match
Interrupt request generated by refresh counter overflow
Note: * SH7750R only
Rev. 6.0, 07/02, page 312 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
