Table 13.3 External Memory Space Map
External
Addresses
Connectable
Memory
Settable Bus
Widths
Area
Size
Access Size
1
*
0
H'00000000–
H'03FFFFFF
64 Mbytes
SRAM
8, 16, 32, 64
8,16,32,
64 6 bits,
*
1
7
*
*
Burst ROM
MPX
8, 16, 32 , 64
32 bytes
1
*
32, 64
2
*
*
1
2
H'04000000–
H'07FFFFFF
64 Mbytes
64 Mbytes
SRAM
8, 16, 32, 64
8,16,32,
64 6 bits,
*
2
*
32, 64
MPX
32 bytes
2
*
16, 32, 64
Byte control SRAM
SRAM
2
H'08000000–
H'0BFFFFFF
8, 16, 32, 64
8,16,32,
64 6 bits,
*
*2 *3
Synchronous DRAM 32, 64
32 bytes
*2 *3
DRAM
MPX
16, 32
32, 64
2
*
2
*
3
H'0C000000–
H'0FFFFFFF
64 Mbytes
SRAM
8, 16, 32, 64
8,16,32,
64 6 bits,
*
*2 *3
Synchronous DRAM 32, 64
32 bytes
*2 *3
DRAM
16, 32, 64
2
*
32, 64
MPX
2
*
4
5
H'10000000–
H'13FFFFFF
64 Mbytes
64 Mbytes
SRAM
8, 16, 32, 64
8,16,32,
64 6 bits,
*
2
*
32, 64
MPX
32 bytes
2
*
16, 32, 64
Byte control RAM
SRAM
2
*
H'14000000–
H'17FFFFFF
8, 16, 32, 64
8,16,32,
64 6 bits,
*
2
*
32, 64
MPX
32 bytes
2
7
*
*
Burst ROM
PCMCIA
SRAM
8, 16, 32 , 64
*2 *4
8, 16
2
*
6
H'18000000–
H'1BFFFFFF
64 Mbytes
64 Mbytes
8, 16, 32, 64
8,16,32,
64 6 bits,
*
2
*
32, 64
MPX
32 bytes
2
*
7
*
Burst ROM
PCMCIA
—
8,16, 32 , 64
*2 *4
8,16
5
*
7
H'1C000000–
—
H'1FFFFFFF
Notes: *1 Memory bus width specified by external pins
*2 Memory bus width specified by register
*3 With synchronous DRAM interface, bus width is 32 or 64 bits only.
With DRAM interface, bus width is 16 or 32 bits only for area 2, and 16, 32, or 64 bits
only for area 3. Bus width of area 2 is as same as that of area 3 which is specified by
MCR.
*4 With PCMCIA interface, bus width is 8 or 16 bits only.
*5 Do not access a reserved area, as operation cannot be guaranteed in this case.
*6 64-bit access applies only to transfer by the DMAC. (CHCRn. TS = 000)
In a transfer to an external memory by FMOV (FPSCR.SZ = 1), two transfer operations,
each with an access size of 32 bits, are conducted.
*7 Settable only for SH7750R.
Rev. 6.0, 07/02, page 320 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
