Bits 8 to 6—CPU Clock Frequency Division Ratio (IFC): These bits specify the CPU clock
frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1
output frequency.
Bit 8: IFC2
Bit 7: IFC1
Bit 6: IFC0
Description
0
0
0
1
0
1
0
1
× 1
× 1/2
1
0
× 1/3
× 1/4
1
× 1/6
× 1/8
Other than the above
Setting prohibited (Do not set)
Bits 5 to 3—Bus Clock Frequency Division Ratio (BFC): These bits specify the bus clock
frequency division ratio with respect to the input clock, 1/2 frequency divider, or PLL circuit 1
output frequency.
Bit 5: BFC2
Bit 4: BFC1
Bit 3: BFC0
Description
0
0
0
1
0
1
0
1
× 1
× 1/2
1
0
× 1/3
× 1/4
1
× 1/6
× 1/8
Other than the above
Setting prohibited (Do not set)
Bits 2 to 0—Peripheral Module Clock Frequency Division Ratio (PFC): These bits specify the
peripheral module clock frequency division ratio with respect to the input clock, 1/2 frequency
divider, or PLL circuit 1 output frequency.
Bit 2: PFC2
Bit 1: PFC1
Bit 0: PFC0
Description
0
0
0
1
0
1
0
× 1/2
× 1/3
1
0
× 1/4
× 1/6
1
× 1/8
Other than the above
Setting prohibited (Do not set)
Rev. 6.0, 07/02, page 256 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
