1. 1-step operation: 1 issue cycle
EXT[SU].[BW], MOV, MOV#, MOVA, MOVT, SWAP.[BW], XTRCT, ADD*, CMP*,
DIV*, DT, NEG*, SUB*, AND, AND#, NOT, OR, OR#, TST, TST#, XOR, XOR#,
ROT*, SHA*, SHL*, BF*, BT*, BRA, NOP, CLRS, CLRT, SETS, SETT,
LDS to FPUL, STS from FPUL/FPSCR, FLDI0, FLDI1, FMOV, FLDS, FSTS,
single-/double-precision FABS/FNEG
D
I
EX
S
NA
2. Load/store: 1 issue cycle
MOV.[BWL]. FMOV*@, LDS.L to FPUL, LDTLB, PREF, STS.L from FPUL/FPSCR
D
I
EX
S
MA
3. GBR-based load/store: 1 issue cycle
MOV.[BWL]@(d,GBR)
D
I
SX
S
MA
4. JMP, RTS, BRAF: 2 issue cycles
D
I
EX
D
S
NA
EX
S
NA
5. TST.B: 3 issue cycles
D
I
SX
D
S
MA
SX
D
S
NA
SX
NA
S
6. AND.B, OR.B, XOR.B: 4 issue cycles
D
I
SX
D
S
MA
SX
D
S
NA
SX
D
NA
SX
S
MA
S
7. TAS.B: 5 issue cycles
D
I
EX
D
S
MA
EX
D
S
NA
EX
D
MA
EX
D
S
NA
EX
S
MA
S
S
8. RTE: 5 issue cycles
D
I
EX
D
S
NA
EX
D
S
NA
EX
D
NA
EX
D
S
NA
EX
S
NA
9. SLEEP: 4 issue cycles
D
I
EX
D
S
NA
EX
D
S
NA
EX
D
NA
EX
S
NA
S
Figure 8.2 Instruction Execution Patterns
Rev. 6.0, 07/02, page 195 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
