19. LDC.L to SR: 4 issue cycles
I
D
EX
D
MA
SX
D
S
SX
D
SX
20. STC from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
D
I
SX
D
S
NA
SX
S
NA
21. STC.L from SGR: 3 issue cycles
D
I
SX
D
S
NA
SX
D
S
NA
SX
NA
S
22. STC.L from DBR/GBR/Rp_BANK/SR/SSR/SPC/VBR: 2 issue cycles
D
I
SX
D
S
NA
SX
S
MA
23. STC.L from SGR: 3 issue cycles
D
I
SX
D
S
NA
SX
D
S
NA
SX
MA
S
24. LDS to PR, JSR, BSRF: 2 issue cycles
I
D
EX
D
NA
SX
S
SX
25. LDS.L to PR: 2 issue cycles
I
D
EX
D
MA
SX
S
SX
26. STS from PR: 2 issue cycles
D
I
SX
D
S
NA
SX
S
S
NA
27. STS.L from PR: 2 issue cycles
D
I
SX
D
S
NA
SX
MA
28. CLRMAC, LDS to MACH/L: 1 issue cycle
D
I
EX
S
NA
F1
F2
F2
FS
FS
F1
29. LDS.L to MACH/L: 1 issue cycle
D
I
EX
S
MA
F1
F1
30. STS from MACH/L: 1 issue cycle
D
I
EX
S
NA
Figure 8.2 Instruction Execution Patterns (cont)
Rev. 6.0, 07/02, page 197 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
