10. OCBI: 1 issue cycle
I
D
EX
MA
MA
S
MA
11. OCBP, OCBWB: 1 issue cycle
I
D
EX
S
MA
MA
MA
MA
MA
MA
MA
12. MOVCA.L: 1 issue cycle
I
D
EX
MA
S
MA
MA
MA
13. TRAPA: 7 issue cycles
I
D
EX
D
NA
EX
D
S
NA
EX
D
S
NA
EX
D
S
NA
EX
D
S
NA
EX
D
S
NA
EX
S
NA
S
14. LDC to DBR/Rp_BANK/SSR/SPC/VBR, BSR: 1 issue cycle
I
D
EX
NA
SX
S
SX
15. LDC to GBR: 3 issue cycles
I
D
EX
D
NA
SX
S
SX
D
16. LDC to SR: 4 issue cycles
I
D
EX
D
NA
SX
D
S
SX
D
SX
17. LDC.L to DBR/Rp_BANK/SSR/SPC/VBR: 1 issue cycle
I
D
EX
MA
SX
S
SX
18. LDC.L to GBR: 3 issue cycles
I
D
EX
D
MA
SX
S
SX
D
Figure 8.2 Instruction Execution Patterns (cont)
Rev. 6.0, 07/02, page 196 of 986
RENESAS [ RENESAS TECHNOLOGY CORP ]
