Section
Page
Item
Description
13.2.8 Memory Control
Register (MCR)
355
Bits 15 to 13—Write
Precharge Delay (TRWL2–
TRWL0)
Description added
358
For Synchronous DRAM
Interface
AMX6 description and
Notes amended
13.2.10 Synchronous DRAM 362 to
Description amended,
and Note added
Mode Register (SDMR)
364
370
371
13.3.1 Endian/Access Size
and Data Alignment
Description amended
Data Configuration
Area 0, Area 1
Quadword partially
amended
13.3.2 Areas
382
387
387
Description added and
amended
13.3.3 SRAM Interface
Basic interface changed
to SRAM interface
Basic Timing
Description amended
388, 393
to 395
Figures 13.6, 13.11 to 13.13 Notes added
395
Read-Strobe Negate Timing Description added and
(Setting Only Possible in the amended
SH7750R)
13.3.4 DRAM Interface
400 to 408 Figures 13.17 to 13.22
Notes added
13.3.5 Synchronous DRAM 413
Interface
Connection of Synchronous
DRAM
Description added
415
Address Multiplexing
Figure 13.28 to 13.37
Description amended
Note added
417 to
428
435
Power-On Sequence
Newly added
438
440
Notes on Changing the Burst Newly added
Length (Variation Only
Possible in the SH7750R)
Connecting a 128-Mbit/256-
Mbit Synchronous DRAM with
64-bit Bus Width
Newly added
13.3.6 Burst ROM Interface 441, 442
Description amended
Notes added
442 to 444 Figure 13.46 to 13.48
Rev. 6.0, 07/02, page xi of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
