Section
13.2.8 Memory Control
Register (MCR)
Page
355
Item
Bits 15 to 13—Write
Precharge Delay (TRWL2–
TRWL0)
For Synchronous DRAM
Interface
Description
Description added
358
13.2.10 Synchronous DRAM 362 to
Mode Register (SDMR)
364
13.3.1 Endian/Access Size
and Data Alignment
13.3.2 Areas
13.3.3 SRAM Interface
370
371
382
387
387
388, 393
to 395
395
AMX6 description and
Notes amended
Description amended,
and Note added
Description amended
Data Configuration
Area 0, Area 1
Quadword partially
amended
Description added and
amended
Basic interface changed
to SRAM interface
Basic Timing
Figures 13.6, 13.11 to 13.13
Read-Strobe Negate Timing
(Setting Only Possible in the
SH7750R)
Connection of Synchronous
DRAM
Address Multiplexing
Figure 13.28 to 13.37
Power-On Sequence
Notes on Changing the Burst
Length (Variation Only
Possible in the SH7750R)
Description amended
Notes added
Description added and
amended
Notes added
Description added
Description amended
Note added
Newly added
Newly added
13.3.4 DRAM Interface
13.3.5 Synchronous DRAM
Interface
400 to 408 Figures 13.17 to 13.22
413
415
417 to
428
435
438
440
Connecting a 128-Mbit/256-
Newly added
Mbit Synchronous DRAM with
64-bit Bus Width
Description amended
Notes added
13.3.6 Burst ROM Interface
441, 442
442 to 444 Figure 13.46 to 13.48
Rev. 6.0, 07/02, page xi of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
