Section
Page
Item
Description
13.3.7 PCMCIA Interface
444, 445
Description amended
and added
446
Table 13.18 Relationship
between Address and CE
when Using PCMCIA
Interface
Table amended
449, 452
to 454
Figures 13.50, 13.53 to 13.55 Notes added
450
Figure 13.51 Wait Timing for SH7750R added to
PCMCIA Memory Card
Interface
Note
451
455
471
Figure 13.52 PCMCIA Space Amended
Allocation
13.3.8 MPX Interface
Description added and
amended
Figure 13.71 MPX Interface Amended
Timing 7
457 to 472 Figures 13.57 to 13.72
473
Notes added
13.3.9 Byte Control SRAM
Interface
Description amended
Notes added
475 to 477 Figures 13.74 to 13.76
13.3.10 Waits between
Access Cycles
479
Figure 13.77 Waits between Replaced
Access Cycles
13.3.11 Bus Arbitration
480, 481
Description added and
amended
13.3.16 Notes on Usage
487
487
Refresh, Bus Arbitration
Description amended
Newly added
Synchronous DRAM Mode
Register Setting (SH7750,
SH7750R Only)
14.1 Overview
14.1.1 Features
489
Description added and
amended
489 to 491
492
Description amended
Title amended
Amended
14.1.2 Block Diagram
(SH7750, SH7750S)
492
Figure 14.1 Block Diagram
of DMAC
14.2 Register Descriptions
(SH7750, SH7750S)
496
Title amended
Rev. 6.0, 07/02, page xii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
