Section
13.3.7 PCMCIA Interface
Page
444, 445
446
Item
Description
Description amended
and added
Table 13.18 Relationship
between Address and CE
when Using PCMCIA
Interface
Table amended
449, 452
to 454
450
Figures 13.50, 13.53 to 13.55 Notes added
Figure 13.51 Wait Timing for SH7750R added to
PCMCIA Memory Card
Note
Interface
Figure 13.52 PCMCIA Space Amended
Allocation
Description added and
amended
Figure 13.71 MPX Interface
Timing 7
Amended
Notes added
Description amended
Notes added
Replaced
Description added and
amended
Refresh, Bus Arbitration
Synchronous DRAM Mode
Register Setting (SH7750,
SH7750R Only)
Description amended
Newly added
Figure 13.77 Waits between
Access Cycles
451
13.3.8 MPX Interface
455
471
457 to 472 Figures 13.57 to 13.72
13.3.9 Byte Control SRAM
Interface
13.3.10 Waits between
Access Cycles
13.3.11 Bus Arbitration
13.3.16 Notes on Usage
473
475 to 477 Figures 13.74 to 13.76
479
480, 481
487
487
14.1 Overview
14.1.1 Features
14.1.2 Block Diagram
(SH7750, SH7750S)
14.2 Register Descriptions
(SH7750, SH7750S)
489
489 to 491
492
492
496
Figure 14.1 Block Diagram
of DMAC
Description added and
amended
Description amended
Title amended
Amended
Title amended
Rev. 6.0, 07/02, page xii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
