Section
Page
Item
Description
14.2.1 DMA Source Address 496
Registers 0–3 (SAR0–SAR3)
Description amended
14.2.2 DMA Destination
Address Registers 0–3
(DAR0–DAR3)
497
Description amended
Description amended
14.2.3 DMA Transfer Count 498
Registers 0–3 (DMATCR0–
DMATCR3)
14.2.4 DMA Channel Control 499
Registers 0–3 (CHCR0–
CHCR3)
Description of DDT
mode added
502, 503
Bits 19 to 16
Bits 15, 14 and Bits 13, 12
Bits 6 to 4
Initial value changed
Description amended
Description added
503
505
508
14.2.5 DMA Operation
Register (DMAOR)
Bit 4
Description amended
14.3.2 DMA Transfer
Requests
513
526
• External Request
Acceptance Conditions
Description added
14.3.4 Types of DMA
Transfer
Table 14.9 External Request Usable DMAC channels
Transfer Sources and
changed
Destinations in DDT Mode
525
(a) Normal DMA Mode
Figure 14.15 to 14.17
Description amendment
14.3.5 Number of Bus Cycle 533 to
Figure description
added
States and '5(4 Pin
535
545
547
Sampling Timing
14.5 On-Demand Data
Transfer Mode (DDT Mode)
Description
amendments
14.5.2 Pins in DDT Mode
%$9/: Data bus D63–D0
Description added
release signal
14.5.3 Transfer Request
Acceptance on Each Channel
551, 552
553
Figures 14.26, 14.27
Figure 14.28
Title amended
Newly added
554
Figure 14.29
Amended
554, 555
Figure 14.30, 14.31
Errors corrected
Description amended
14.5.4 Notes on Use of DDT 572
Module
c. of 3. Handshake protocol
using the data bus (valid on
channel 0 only)
573
573
b. of 8. Data transfer end
request
Added
12. Confirming DMA transfer Description amended
requests and number of
transfers executed
Rev. 6.0, 07/02, page xiii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
