Section
Page
Item
Table 13.2 BSC Registers
Description
Bus control register 3
and 4 added to table,
and Note added
64
*
added to Area 0, 5,
6 Settable Bus Widths,
and Note 7 added
Description amended
Table amended, and
Notes amended and
added
Description added
Bit 18 amended and
note added
Description added
Description and notes
added
Description amended
Table amended and
note added
7
13.1.4 Register Configuration 318
13.1.5 Overview of Areas
320
Table 13.3 External Memory
Space Map
Space Divisions
Table 13.3 External Memory
Space Map
Memory Bus Width
Bit table
Bit 31, Bit 30, Bit 29
Bit 26
Bit 16
Bit 15, Bit 14
Bits 13 to 11
Bits 10 to 8
Bits 7 to 5
Bit 0
Bits 15, 14
319
320
321, 322
13.2.1 Bus Control Register
1 (BCR1)
326
327
328
330
330
331
332
333
334
13.2.2 Bus Control Register
2 (BCR2)
13.2.3 Bus Control Register
3 (BCR3) (SH7750R Only)
13.2.4 Bus Control Register
4 (BCR4)
13.2.5 Wait Control Register
1 (WCR1)
13.2.6 Wait Control Register
2 (WCR2)
335
337
338
338,
339
342
344 to
349
Description amended
Description added
Newly added
Bits 12 to 1—Reserved
Description added
Newly added
Note amended
Bits 31 to 29, Bits 25 to 23,
Bits 19 to 17, Bits 15 to 13,
Bits 11 to 9, Bits 8 to 6,
Bits 5 to 3, and Bits 2 to 0
Bit table
Description added and
amended
13.2.7 Wait Control Register
3 (WCR3)
351
351
Bits 19 and 7 changed,
and Note added
Description added
Rev. 6.0, 07/02, page x of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
