Section
Page
Item
Description
13.1.4 Register Configuration 318
Table 13.2 BSC Registers
Bus control register 3
and 4 added to table,
and Note added
Table 13.3 External Memory 64 7 added to Area 0, 5,
*
13.1.5 Overview of Areas
320
Space Map
6 Settable Bus Widths,
and Note 7 added
319
320
Space Divisions
Description amended
Table 13.3 External Memory Table amended, and
Space Map
Notes amended and
added
321, 322
Memory Bus Width
Bit table
Description added
13.2.1 Bus Control Register 326
1 (BCR1)
Bit 18 amended and
note added
327
328
330
330
331
332
333
334
Bit 31, Bit 30, Bit 29
Bit 26
Description added
Description and notes
added
Bit 16
Bit 15, Bit 14
Bits 13 to 11
Bits 10 to 8
Bits 7 to 5
Bit 0
Description amended
Table amended and
note added
Description amended
Description added
13.2.2 Bus Control Register 335
2 (BCR2)
Bits 15, 14
13.2.3 Bus Control Register 337
Newly added
3 (BCR3) (SH7750R Only)
338
Bits 12 to 1—Reserved
Description added
Newly added
13.2.4 Bus Control Register 338,
4 (BCR4)
339
13.2.5 Wait Control Register 342
1 (WCR1)
Note amended
13.2.6 Wait Control Register 344 to
Bits 31 to 29, Bits 25 to 23,
Bits 19 to 17, Bits 15 to 13,
Bits 11 to 9, Bits 8 to 6,
Description added and
amended
2 (WCR2)
349
Bits 5 to 3, and Bits 2 to 0
13.2.7 Wait Control Register 351
3 (WCR3)
Bit table
Bits 19 and 7 changed,
and Note added
351
Description added
Rev. 6.0, 07/02, page x of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
