Section
5.6.3 Interrupts
7.3 Instruction Set
8.3 Execution Cycles and
Pipeline Stalling
9.1.1 Types of Power-Down
Modes
Page
157
186
204 to
206
222
Item
(3) Peripheral Module
Interrupts
Description
Description changed
Table 7.7 Branch Instructions Description added
Description amended
Note changed
Table 9.1 Status of CPU and Hardware standby
Peripheral Modules in Power- (SH7750S, SH7750R)
Down Modes
added to table,
description amended
Table 9.2 Power-Down Mode Description and Note
Registers
added to table
Table 9.3 Power-Down Mode Description added to
Pins
Function in table and
amended
Other information
Other Information
Bit table
Description amended
Added
Bit 6 amended to STHZ
and bit 1 to MSTP6,
note added
Description added
Newly added
Added
9.1.2 Register Configuration
9.1.3 Pin Configuration
223
223
9.2.2 Peripheral Module Pin
High Impedance Control
9.2.3 Peripheral Module Pin
Pull-Up Control
9.2.4 Standby Control
Register 2 (STBCR2)
226
226
227
227
9.2.5 Clock-Stop Register 00 228, 229
(CLKSTP00) (SH7750R Only)
9.2.6 Clock-Stop Clear
229
Register 00 (CLKSTPCLR00)
(SH7750R Only)
9.4.1 Transition to Deep
Sleep Mode
9.5.2 Exit from Standby
Mode
9.6.1 Transition to Module
Standby Function
9.6.2 Exit from Module
Standby Function
230
232
234
Bit 6, Bits 1 and 0
Description amended,
Note added
Exit by Interrupt
Note added
Text amended
Table description and
note added
234
Description amended
Note deleted
SH7750R added
9.7 Hardware Standby Mode 235
(SH7750S, SH7750R Only)
Rev. 6.0, 07/02, page vii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
