Section
Page
Item
Description
5.6.3 Interrupts
157
(3) Peripheral Module
Interrupts
Description changed
7.3 Instruction Set
186
Table 7.7 Branch Instructions Description added
Description amended
8.3 Execution Cycles and
Pipeline Stalling
204 to
206
9.1.1 Types of Power-Down
Modes
Note changed
222
Table 9.1 Status of CPU and Hardware standby
Peripheral Modules in Power- (SH7750S, SH7750R)
Down Modes
added to table,
description amended
9.1.2 Register Configuration 223
9.1.3 Pin Configuration 223
Table 9.2 Power-Down Mode Description and Note
Registers added to table
Table 9.3 Power-Down Mode Description added to
Pins
Function in table and
amended
9.2.2 Peripheral Module Pin 226
High Impedance Control
Other information
Other Information
Bit table
Description amended
9.2.3 Peripheral Module Pin 226
Pull-Up Control
Added
9.2.4 Standby Control
Register 2 (STBCR2)
227
Bit 6 amended to STHZ
and bit 1 to MSTP6,
note added
227
Bit 6, Bits 1 and 0
Description added
Newly added
9.2.5 Clock-Stop Register 00 228, 229
(CLKSTP00) (SH7750R Only)
9.2.6 Clock-Stop Clear
Register 00 (CLKSTPCLR00)
(SH7750R Only)
229
Added
9.4.1 Transition to Deep
Sleep Mode
230
232
234
Description amended,
Note added
9.5.2 Exit from Standby
Mode
Exit by Interrupt
Note added
9.6.1 Transition to Module
Standby Function
Text amended
Table description and
note added
9.6.2 Exit from Module
Standby Function
234
Description amended
Note deleted
9.7 Hardware Standby Mode 235
(SH7750S, SH7750R Only)
SH7750R added
Rev. 6.0, 07/02, page vii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
