Section
Page
Item
Description
9.8.5 Hardware Standby
Mode Timing (SH7750S,
SH7750R Only)
244 to
246
Figures 9.12, 9.13, 9.15
Figures changed
Notes added
10.2.1 Block Diagram of
CPG
249
Figure 10.1 (1) Block
Diagram of CPG (SH7750,
SH7750S)
Amended
250
252
252
Figure 10.1 (2) Block
Diagram of CPG (SH7750R)
Newly added
10.2.2 CPG Pin
Configuration
Table 10.1 CPG Pins
Table and Note
amended
10.2.3 CPG Register
Configuration
Table 10.2 CPG Register
Description added
10.3 Clock Operating Modes
Description added and
amended
253
Table 10.3 (1) Clock
Operating Modes (SH7750,
SH7750S)
Table amended and
Note amended and
added
253
254
Table 10.3 (2) Clock
Operating Modes (SH7750R)
Newly added
Table 10.4 FRQCR Settings Table and Note
and Internal Clock
Frequencies
amended
10.8.2 Watchdog Timer
Control/Status Register
(WTCSR)
261
Description amended
10.10 Notes on Board
Design
265
266
When Using a PLL Oscillator Description amended
Circuit
Figure 10.5 Points for
Attention when Using PLL
Oscillator Circuit
Amended
11.1.1 Features
267
268
269
Description added for
Alarm interrupts
11.1.2 Block Diagram
11.1.3 Pin Configuration
Figure 11.1 Block Diagram
of RTC
Figure amended and
Note added
Table 11.1 RTC Pins
Table amended
11.1.4 Register Configuration 270
Table 11.2 RTC Registers
RTC control register 3
and Year alarm register
added to table, and
Note added
Rev. 6.0, 07/02, page viii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
