Section
9.8.5 Hardware Standby
Mode Timing (SH7750S,
SH7750R Only)
10.2.1 Block Diagram of
CPG
Page
244 to
246
249
Item
Figures 9.12, 9.13, 9.15
Description
Figures changed
Notes added
Figure 10.1 (1) Block
Diagram of CPG (SH7750,
SH7750S)
Figure 10.1 (2) Block
Diagram of CPG (SH7750R)
Table 10.1 CPG Pins
Table 10.2 CPG Register
Amended
250
10.2.2 CPG Pin
Configuration
10.2.3 CPG Register
Configuration
10.3 Clock Operating Modes
253
252
252
Newly added
Table and Note
amended
Description added
Description added and
amended
Table 10.3 (1) Clock
Operating Modes (SH7750,
SH7750S)
Table amended and
Note amended and
added
253
254
Table 10.3 (2) Clock
Newly added
Operating Modes (SH7750R)
Table 10.4 FRQCR Settings
and Internal Clock
Frequencies
Table and Note
amended
Description amended
10.8.2 Watchdog Timer
Control/Status Register
(WTCSR)
10.10 Notes on Board
Design
261
265
266
When Using a PLL Oscillator
Circuit
Figure 10.5 Points for
Attention when Using PLL
Oscillator Circuit
Description amended
Amended
11.1.1 Features
11.1.2 Block Diagram
11.1.3 Pin Configuration
267
268
269
Figure 11.1 Block Diagram
of RTC
Table 11.1 RTC Pins
Table 11.2 RTC Registers
Description added for
Alarm interrupts
Figure amended and
Note added
Table amended
RTC control register 3
and Year alarm register
added to table, and
Note added
11.1.4 Register Configuration 270
Rev. 6.0, 07/02, page viii of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
