Section
Page
Item
Description
19.2.4 Interrupt Exception
Handling and Priority
758
Description added
Description added to
Exception Handling Sources table, Notes added and
and Priority Order amended
759 to
761
Table 19.5 Interrupt
19.3.1 Interrupt Priority
Registers A to D (IPRA–
IPRD)
762
Table 19.6 Interrupt Request SH7750R added to
Sources and IPRA–IPRD
Registers
Note 3
19.3.3 Interrupt-Priority-Level 764
Setting Register 00
Newly added
(INTPRI00)
19.3.4 Interrupt Source
Register 00 (INTREQ00)
(SH7750R Only)
765
766
Newly added
19.3.5 Interrupt Mask
Register 00 (INTMSK00)
(SH7750R Only)
Newly added
19.3.6 Interrupt Mask Clear 767
Register 00 (INTMSKCLR00)
(SH7750R Only)
Newly added
19.3.7 Bit Assignments of
INTREQ00, INTMSK00, and
INTMSKCLR00 (SH7750R
Only)
767
19.3.4 moved to 19.3.7
19.4.1 Interrupt Operation
Sequence
768
771
Note 3 added
19.5 Interrupt Response
Time
Note amended
Description added
Description added
4. Description added
Amended
20.2.4 Break Address Mask 778, 779
Register (BAMRA)
Bit 2, and Bits 3, 1, and 0
Bits 31 to 0
20.2.10 Break Data Mask
Register B (BDMRB)
783
791
794
20.3.7 Program Counter
(PC) Value Saved
20.3.7 Program Counter
(PC) Value Saved
20.4 User Break Debug
Support Function
Figure 20.2 User Break
Debug Support Function
Flowchart
21.1.1 Features
799
800
Description amended
21.1.2 Block Diagram
Figure 21.1 Block Diagram
of H-UDI Circuit
Figure changed and
Note added
Rev. 6.0, 07/02, page xv of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
