Section
Page
Item
Description
3.3.3 Virtual Address Space 68, 69
Description changed
Description changed
Note added
3.3.4 On-Chip RAM Space
69
70
3.3.7 Address Space
Identifier (ASID)
4.1.1 Features
Completely revised
Completely revised
95
95
96
97
97
Table 4.1 Cache Features
(SH7750, SH7750S)
Table 4.2 Cache Features
(SH7750R)
Newly added
Table 4.3 Features of Store Description added
Queues
4.2 Register Descriptions
Figure 4.1 Cache and Store Figure changed and
Queue Control Registers
Note added
(1) Cache Control Register
(CCR)
Description added and
amended
4.3.1 Configuration
4.3.6 RAM Mode
Description added
Newly added
101
Figure 4.3 Configuration of
Operand Cache (SH7750R)
106 to
107
Description amended
and added
4.3.7 OC Index Mode
4.4.1 Configuration
107
109
Description added
Figure 4.5 amended to
figure 4.6, description
added and amended
110
Figure 4.7 Configuration of
Instruction Cache (SH7750R)
Newly added
4.6 Memory-Mapped Cache 116
Configuration (SH7750R)
Newly added
4.7 Store Queues
122
Description amended
and added
4.7.3 Transfer to External
Memory
122, 123
Description added
4.7.4 SQ Protection
124
124
Description added
Newly added
4.7.5 Reading the SQs
(SH7750R Only)
4.7.6 SQ Usage Notes
125
128
Newly added
5.2 Register Descriptions
Description amended
5.4 Exception Types and
Priorities
130 to
132
Table 5.2 Exceptions
Description and note
added
Rev. 6.0, 07/02, page vi of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
