Section
3.3.3 Virtual Address Space
3.3.4 On-Chip RAM Space
3.3.7 Address Space
Identifier (ASID)
4.1.1 Features
Page
68, 69
69
70
Item
Description
Description changed
Description changed
Note added
Completely revised
95
95
96
4.2 Register Descriptions
97
97
4.3.1 Configuration
101
4.3.6 RAM Mode
4.3.7 OC Index Mode
4.4.1 Configuration
106 to
107
107
109
Table 4.1 Cache Features
(SH7750, SH7750S)
Table 4.2 Cache Features
(SH7750R)
Table 4.3 Features of Store
Queues
Figure 4.1 Cache and Store
Queue Control Registers
(1) Cache Control Register
(CCR)
Figure 4.3 Configuration of
Operand Cache (SH7750R)
Completely revised
Newly added
Description added
Figure changed and
Note added
Description added and
amended
Description added
Newly added
Description amended
and added
Description added
Figure 4.5 amended to
figure 4.6, description
added and amended
110
4.6 Memory-Mapped Cache
Configuration (SH7750R)
4.7 Store Queues
4.7.3 Transfer to External
Memory
4.7.4 SQ Protection
4.7.5 Reading the SQs
(SH7750R Only)
4.7.6 SQ Usage Notes
5.2 Register Descriptions
5.4 Exception Types and
Priorities
116
122
122, 123
124
124
125
128
130 to
132
Figure 4.7 Configuration of
Newly added
Instruction Cache (SH7750R)
Newly added
Description amended
and added
Description added
Description added
Newly added
Newly added
Description amended
Table 5.2 Exceptions
Description and note
added
Rev. 6.0, 07/02, page vi of I
RENESAS [ RENESAS TECHNOLOGY CORP ]
